Hello,

More of my philosophy about the 16 sockets HPE Integrity Superdome X from Hewlett Packard Enterprise from USA and more of my thoughts..

I am a white arab, and i think i am smart since i have also
invented many scalable algorithms and algorithms..

I think i am highly smart since I have passed two certified IQ tests and i have scored "above" 115 IQ, so i think that parallel programming with memory on Intel's CXL will be different than parallel programming the many memory channels and on many sockets, so i think so that to scale much more the memory channels on many sockets and be compatible, i advice you to for example buy the 16 sockets HPE Integrity Superdome X from Hewlett Packard Enterprise from USA here:

https://cdn.cnetcontent.com/3b/dc/3bdcd896-f2b4-48e4-bbf6-a75234db25da.pdf

And i am sure that my below Powerful Open source software project of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well will work correctly on the 16 sockets HPE Integrity Superdome X from Hewlett Packard Enterprise from USA.

More of my philosophy about the future of system memory and more of thoughts..

Here is the future of system memory of how to scale like with many more memory channels:

THE FUTURE OF SYSTEM MEMORY IS MOSTLY CXL

Read more here:

https://www.nextplatform.com/2022/07/05/the-future-of-system-memory-is-mostly-cxl/

So i think the way to parallel programming in the standard Intel’s CXL will be the same as programming with many memory channels as i am
doing it below with my Powerful Open source software project of Parallel C++ Conjugate Gradient Linear System Solver Library that scales very well.

More of my philosophy about x86 CPUs and about cache prefetching and more of my thoughts..

I think i am highly smart since I have passed two certified IQ tests and i have scored "above" 115 IQ, and today i will talk about the how to prefetch data into the caches on x86 microprocessors:

So here my following delphi and freepascal x86 inline assembler procedures that prefetch data into the caches:

So for 32 bit Delphi and Freepascal compilers, here is how to prefetch data into the level 1 cache and notice that, in delphi and freepascal compilers, when we pass the first parameter of the procedure with a register convention, it will be passed on CPU register eax of the x86 microprocessor:

procedure Prefetch(p : pointer); register;
asm
prefetchT1 byte ptr [eax]
end;

For 64 bit Delphi and Freepascal compilers, here is how to prefetch data into the level 1 cache and notice that, in delphi and freepascal compilers, when we pass the first parameter of the procedure with a register convention, it will be passed on CPU register rcx of the x86 microprocessor:

procedure Prefetch(p : pointer); register;
asm
prefetchT1 byte ptr [rcx]
end;

And you can request a loading of 256 bytes in advance into the caches, and it can be efficient, by doing this:

So for 32 bit Delphi and Freepascal compilers you do this:

procedure Prefetch(p : pointer); register;
asm
prefetchT1 byte ptr [eax]+256
end;

So for 64 bit Delphi and Freepascal compilers you do this:

procedure Prefetch(p : pointer); register;
asm
prefetchT1 byte ptr [rcx]+256
end;

So you can also prefetch into level 0 and level 2 caches with the x86 assembler instruction prefetchT0 and prefetchT2, so just replace, in the above inline assembler procedures, prefetchT1 with prefetchT0 or prefetchT2, but i think i am highly smart and i say that notice that those prefetch x86 assembler instructions are used since also the microprocessor can be faster than memory, so then you have to understand that today, the story is much nicer, since the powerful x86 processor cores can all sustain many memory requests, and we call this process: "memory-level parallelism", and today x86 AMD or Intel processor cores could support more than 10 independent memory requests at a time, so for example Graviton 3 ARM CPU appears to sustain about 19 simultaneous memory loads per core against about 25 for the Intel processor, so then i think i can also say that this memory-level parallelism looks like using latency hiding so that to speed the things more so that the CPU doesn't wait too much for memory.

And now i invite you to read more of my thoughts about stack memory allocations and about preemptive and non-preemptive timesharing in the following web link:

https://groups.google.com/g/alt.culture.morocco/c/JuC4jar661w

And more of my philosophy about Stacktrace and more of my thoughts..

I think i am highly smart, and i say that there is advantages and disadvantages to portability in software programming , for example you can make your application run just in Windows operating system and it can be much more business friendly than making it run in multiple operating systems, since in business you have for example to develop and sell your application faster or much faster than the competition, so then we can not say that the tendency of C++ to requiring portability is a good thing.

Other than that i have just looked at Delphi and Freepascal and
i have just noticed that the Stacktrace in Freepascal is much more enhanced than Delphi, since look for example at the following application of Freepascal that has made Stacktrace portable to different operating systems and CPU architectures , and it is a much more enhanced stacktrace that is better than the Delphi ones that run just in Windows:

https://github.com/r3code/lazarus-exception-logger

But notice carefully that the Delphi ones run just in Windows:

https://docwiki.embarcadero.com/Libraries/Sydney/en/System.SysUtils.Exception.StackTrace

So i think that since a much more enhanced Stacktrace is important,
so i think that Delphi needs to provide us with a portable one to different operating systems and CPU architectures.

Also the Free Pascal Developer team is pleased to finally announce the addition of a long awaited feature, though to be precise it's two different, but very much related features: Function References and Anonymous Functions. These two features can be used independantly of each other, but their greatest power they unfold when used together.

Read about it here:

https://forum.lazarus.freepascal.org/index.php/topic,59468.msg443370.html#msg443370

More of my philosophy about the AMD Epyc CPU and more of my thoughts..

I think i am highly smart since I have passed two certified IQ tests and i have scored "above" 115 IQ, if you want to be serious about buying
a CPU and motherboard, i advice you to buy the following AMD Epyc 7313p Milan 16 cores CPU that costs much less(around 1000 US dollars) and that is reliable and fast, since it is a 16 cores CPU and it supports standard ECC memory and it supports 8 memory channels, here it is:

https://en.wikichip.org/wiki/amd/epyc/7313p

And the good Supermicro motherboard for it that supports the Epyc Milan 7003 is the following:

https://www.newegg.com/supermicro-mbd-h12ssl-nt-o-supports-single-amd-epyc-7003-7002-series-processor/p/1B4-005W-00911?Description=amd%20epyc%20motherboard&cm_re=amd_epyc%20motherboard-_-1B4-005W-00911-_-Product

And the above AMD Epyc 7313p Milan 16 cores CPU can be configured
as NUMA using the good Supermicro motherboard above as following:

This setting enables a trade-off between minimizing local memory latency for NUMAaware or highly parallelizable workloads vs. maximizing per-core memory bandwidth for non-NUMA-friendly workloads. The default configuration (one NUMA domain per socket) is recommended for most workloads. NPS4 is recommended for HPC and other highly parallel workloads.Here is the detail introduction for such options:

• NPS0: Interleave memory accesses across all channels in both sockets (not recommended)

• NPS1: Interleave memory accesses across all eight channels in each socket, report one NUMA node per socket (unless L3 Cache as NUMA is enabled)

• NPS2: Interleave memory accesses across groups of four channels (ABCD and EFGH) in each socket, report two NUMA nodes per socket (unless L3 Cache as NUMA is enabled)

• NPS4: Interleave memory accesses across pairs of two channels (AB, CD, EF and GH) in each socket, report four NUMA nodes per socket (unless L3 Cache as NUMA is enabled)

And of course you have to read my following writing about DDR5 memory that is not a fully ECC memory:

"On-die ECC: The presence of on-die ECC on DDR5 memory has been the subject of many discussions and a lot of confusion among consumers and the press alike. Unlike standard ECC, on-die ECC primarily aims to improve yields at advanced process nodes, thereby allowing for cheaper DRAM chips. On-die ECC only detects errors if they take place within a cell or row during refreshes. When the data is moved from the cell to the cache or the CPU, if there’s a bit-flip or data corruption, it won’t be corrected by on-die ECC. Standard ECC corrects data corruption within the cell and as it is moved to another device or an ECC-supported SoC."

Read more here to notice it:

https://www.hardwaretimes.com/ddr5-vs-ddr4-ram-quad-channel-and-on-die-ecc-explained/

So if you want to get serious and professional you can buy the above
AMD Epyc 7313p Milan 16 cores CPU with the Supermicro motherboard that supports it and that i am advicing and that supports the fully ECC memory and that supports 8 memory channels.

And of course you can read my thoughts about technology in the following web link:

https://groups.google.com/g/soc.culture.usa/c/N_UxX3OECX4

And of course you have to read my following thoughts that also show how
powerful is to use 8 memory channels: