Johnny Billquist <bqt@softjar.se> writes:

> On 2023-09-04 13:02, Thomas Koenig wrote:
>
> The PDP-11 (at least some models) have the exact same behavior with
> the registers. The CPU registers do exist in memory space, and you can
> run code in them.

I don't remember ever coming across this -- which models?

Joe Pfeiffer <pfeiffer@cs.nmsu.edu> wrote:
> Johnny Billquist <bqt@softjar.se> writes:
>
>> On 2023-09-04 13:02, Thomas Koenig wrote:
>>
>> The PDP-11 (at least some models) have the exact same behavior with
>> the registers. The CPU registers do exist in memory space, and you can
>> run code in them.
>
> I don't remember ever coming across this -- which models?
>

I do think Xerox/SDS Sigma systems had this. The IBM 1130 had its index
registers in core (not backing real registers, although the 1800 did have
real registers too).

--
Pete

Peter Flass <peter_flass@yahoo.com> writes:

> Joe Pfeiffer <pfeiffer@cs.nmsu.edu> wrote:
>> Johnny Billquist <bqt@softjar.se> writes:
>>
>>> On 2023-09-04 13:02, Thomas Koenig wrote:
>>>
>>> The PDP-11 (at least some models) have the exact same behavior with
>>> the registers. The CPU registers do exist in memory space, and you can
>>> run code in them.
>>
>> I don't remember ever coming across this -- which models?
>>
>
> I do think Xerox/SDS Sigma systems had this. The IBM 1130 had its index
> registers in core (not backing real registers, although the 1800 did have
> real registers too).

Yes, there were several other computer families that did it. It's
specifically PDP 11 where I haven't heard of it before.

Johnny Billquist wrote:
> I guess that might imply that the PDP-6 also had the registers in main
> memory.

There was a "fast memory" option to implement the accumulator storage
with flip-flops rather than core. I'm not sure about the details; it might have
been the first device on the memory bus.

On 2023-09-06 17:49, Joe Pfeiffer wrote:
> Johnny Billquist <bqt@softjar.se> writes:
>
>> On 2023-09-04 13:02, Thomas Koenig wrote:
>>
>> The PDP-11 (at least some models) have the exact same behavior with
>> the registers. The CPU registers do exist in memory space, and you can
>> run code in them.
>
> I don't remember ever coming across this -- which models?

I won't dare trying to list them all. I know that the 11/70 have it,
which implies that the 11/45, 11/50 and 11/55 also do. My guess is that
all PDP-11s, except those that have a serial console built into the CPU.
So anything except the F11 and J11 based. Possibly also T11.

General register set 0 is at 17777700 to 17777707. General register set
1 is at 17777710 to 17777717. The weird/funny thing is that when you
access these addresses on the front panel, addresses actually increment
by 1, and not the usual 2. But they are still 16 bit data on each
address (obviously, since they are the CPU registers).

It's all documented in the processor handbook. Some PDP-11 models allow
you to access the general registers in the I/O page, but do not allow
you to run from them, while others do. And some models to not have the
registers visible there at all. So it is rather model dependent.

This is a rather obscure piece of knowledge though, and I'm not
surprised most people are not aware. But think about it - if you have a
PDP-11 with a front panel, this is the only way to find out what content
you have in your CPU registers...

Johnny

Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes:
>Peter Flass <peter_flass@yahoo.com> writes:
>
>> Joe Pfeiffer <pfeiffer@cs.nmsu.edu> wrote:
>>> Johnny Billquist <bqt@softjar.se> writes:
>>>
>>>> On 2023-09-04 13:02, Thomas Koenig wrote:
>>>>
>>>> The PDP-11 (at least some models) have the exact same behavior with
>>>> the registers. The CPU registers do exist in memory space, and you can
>>>> run code in them.
>>>
>>> I don't remember ever coming across this -- which models?
>>>
>>
>> I do think Xerox/SDS Sigma systems had this. The IBM 1130 had its index
>> registers in core (not backing real registers, although the 1800 did have
>> real registers too).
>
>Yes, there were several other computer families that did it. It's
>specifically PDP 11 where I haven't heard of it before.

Indeed, the Burroughs BCD machines also had their index registers
in low memory.

On Thursday, August 31, 2023 at 4:37:55 AM UTC-6, Theo Markettos wrote:
> Elijah Stone <elr...@elronnd.net> wrote:
> > I am looking for information on the history and development of ISAs as a
> > technology. Including:
> >
> > - Why were they invented? (IBM wanted to sell their customers hardware
> > upgrades without requiring that they rewrite their code?)

> I think this is slightly the wrong question. Every stored program computer
> has an ISA, being the encoding of stored instructions to logical operations.
> In the early days the ISA was unique to the machine, but the machines
> started as one-offs anyway.

But given his reference to IBM, apparently he is thinking of the ISA as existing
as a "thing" only when it is shared by more than one model of a computer.

Since the EDSAC and the EDVAC, built separately according to the same plan,
shared an instruction set, but were also basically the same implementation, I'm
not sure they would count by his standards.

Before the IBM 360, the IBM 709 was upwards-compatible with the IBM 704,
and Univac made the 1103 and the 1103A.

The SDS 910, 920, and 930 were a series of three machines of different sizes
available from Scientific Data Systems which shared an instruction set for a
24-bit word. And the GE 225 and 235 were part of a compatible series with a
20 bit word also.

John Savard

On 2023-09-07, Scott Lurndal <scott@slp53.sl.home> wrote:

> Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes:
>
>> Peter Flass <peter_flass@yahoo.com> writes:
>>
>>> Joe Pfeiffer <pfeiffer@cs.nmsu.edu> wrote:
>>>
>>>> Johnny Billquist <bqt@softjar.se> writes:
>>>>
>>>>> On 2023-09-04 13:02, Thomas Koenig wrote:
>>>>>
>>>>> The PDP-11 (at least some models) have the exact same behavior with
>>>>> the registers. The CPU registers do exist in memory space, and you can
>>>>> run code in them.
>>>>
>>>> I don't remember ever coming across this -- which models?
>>>
>>> I do think Xerox/SDS Sigma systems had this. The IBM 1130 had its index
>>> registers in core (not backing real registers, although the 1800 did have
>>> real registers too).
>>
>> Yes, there were several other computer families that did it. It's
>> specifically PDP 11 where I haven't heard of it before.
>
> Indeed, the Burroughs BCD machines also had their index registers
> in low memory.

The Univac 9300 (their answer to the IBM 360/20) also stored its
registers in low memory. Two sets, actually, to support its primitive
version of problem and supervisor states. Its equivalent of the 360's
PSW was also in low memory. I had fun writing little programs that
did strange things, e.g. fill memory with an instruction that decremented
the program counter by 8, jump to the last one, and execute the program
backwards.

--
/~\ Charlie Gibbs | They offer a huge range of
\ / <cgibbs@kltpzyxm.invalid> | world-class vulnerabilities
X I'm really at ac.dekanfrus | that only Microsoft can provide.
/ \ if you read it the right way. | -- druck

On Thu, 07 Sep 2023 13:14:30 +0000, Scott Lurndal wrote:

> Joe Pfeiffer <pfeiffer@cs.nmsu.edu> writes:
>>Peter Flass <peter_flass@yahoo.com> writes:
>>
>>> Joe Pfeiffer <pfeiffer@cs.nmsu.edu> wrote:
>>>> Johnny Billquist <bqt@softjar.se> writes:
>>>>
>>>>> On 2023-09-04 13:02, Thomas Koenig wrote:
>>>>>
>>>>> The PDP-11 (at least some models) have the exact same behavior with
>>>>> the registers. The CPU registers do exist in memory space, and you
>>>>> can run code in them.
>>>>
>>>> I don't remember ever coming across this -- which models?
>>>>
>>>>
>>> I do think Xerox/SDS Sigma systems had this. The IBM 1130 had its
>>> index registers in core (not backing real registers, although the 1800
>>> did have real registers too).
>>
>>Yes, there were several other computer families that did it. It's
>>specifically PDP 11 where I haven't heard of it before.
>
> Indeed, the Burroughs BCD machines also had their index registers in low
> memory.

And the ICT 1900 (physically on the lower end of the range).

--
Using UNIX since v6 (1975)...

Use the BIG mirror service in the UK:
http://www.mirrorservice.org

Johnny Billquist <bqt@softjar.se> writes:

> On 2023-09-06 17:49, Joe Pfeiffer wrote:
>> Johnny Billquist <bqt@softjar.se> writes:
>>
>>> On 2023-09-04 13:02, Thomas Koenig wrote:
>>>
>>> The PDP-11 (at least some models) have the exact same behavior with
>>> the registers. The CPU registers do exist in memory space, and you can
>>> run code in them.
>> I don't remember ever coming across this -- which models?
>
> I won't dare trying to list them all. I know that the 11/70 have it,
> which implies that the 11/45, 11/50 and 11/55 also do. My guess is
> that all PDP-11s, except those that have a serial console built into
> the CPU. So anything except the F11 and J11 based. Possibly also T11.
>
> General register set 0 is at 17777700 to 17777707. General register
> set 1 is at 17777710 to 17777717. The weird/funny thing is that when
> you access these addresses on the front panel, addresses actually
> increment by 1, and not the usual 2. But they are still 16 bit data on
> each address (obviously, since they are the CPU registers).

Yes, I was just able to verify this. Cool!

Quadibloc <jsavard@ecn.ab.ca> wrote:
> On Thursday, August 31, 2023 at 4:37:55 AM UTC-6, Theo Markettos wrote:
>> Elijah Stone <elr...@elronnd.net> wrote:
>>> I am looking for information on the history and development of ISAs as a
>>> technology. Including:
>>>
>>> - Why were they invented? (IBM wanted to sell their customers hardware
>>> upgrades without requiring that they rewrite their code?)
>
>> I think this is slightly the wrong question. Every stored program computer
>> has an ISA, being the encoding of stored instructions to logical operations.
>> In the early days the ISA was unique to the machine, but the machines
>> started as one-offs anyway.
>
> But given his reference to IBM, apparently he is thinking of the ISA as existing
> as a "thing" only when it is shared by more than one model of a computer.
>
> Since the EDSAC and the EDVAC, built separately according to the same plan,
> shared an instruction set, but were also basically the same implementation, I'm
> not sure they would count by his standards.
>
> Before the IBM 360, the IBM 709 was upwards-compatible with the IBM 704,
> and Univac made the 1103 and the 1103A.
>
> The SDS 910, 920, and 930 were a series of three machines of different sizes
> available from Scientific Data Systems which shared an instruction set for a
> 24-bit word. And the GE 225 and 235 were part of a compatible series with a
> 20 bit word also.
>

I wasn’t aware of the incompatibilities among various PDP-11 models, but
the -10s seemed to have areas of incompatibility also. I believe IBM was
the first to define an “architecture” independent of any particular
implementation, and then make sure (nearly) all S/360 models conformed to
it.

--
Pete

Peter Flass <peter_flass@yahoo.com> writes:
>Quadibloc <jsavard@ecn.ab.ca> wrote:
>> On Thursday, August 31, 2023 at 4:37:55 AM UTC-6, Theo Markettos wrote:
>>> Elijah Stone <elr...@elronnd.net> wrote:
>>>> I am looking for information on the history and development of ISAs as a
>>>> technology. Including:
>>>>
>>>> - Why were they invented? (IBM wanted to sell their customers hardware
>>>> upgrades without requiring that they rewrite their code?)
>>
>>> I think this is slightly the wrong question. Every stored program computer
>>> has an ISA, being the encoding of stored instructions to logical operations.
>>> In the early days the ISA was unique to the machine, but the machines
>>> started as one-offs anyway.
>>
>> But given his reference to IBM, apparently he is thinking of the ISA as existing
>> as a "thing" only when it is shared by more than one model of a computer.
>>
>> Since the EDSAC and the EDVAC, built separately according to the same plan,
>> shared an instruction set, but were also basically the same implementation, I'm
>> not sure they would count by his standards.
>>
>> Before the IBM 360, the IBM 709 was upwards-compatible with the IBM 704,
>> and Univac made the 1103 and the 1103A.
>>
>> The SDS 910, 920, and 930 were a series of three machines of different sizes
>> available from Scientific Data Systems which shared an instruction set for a
>> 24-bit word. And the GE 225 and 235 were part of a compatible series with a
>> 20 bit word also.
>>
>
>I wasn’t aware of the incompatibilities among various PDP-11 models, but
>the -10s seemed to have areas of incompatibility also. I believe IBM was
>the first to define an “architecture” independent of any particular
>implementation, and then make sure (nearly) all S/360 models conformed to
>it.

Burroughs early architectures (medium and large systems (B6xxx and successor))
were independent of any particular implementation. And like the 360 family,
new features were added to the architecture to provide new capabilities in
a backward compatable fashion. The B3500 was roughly contemporaneous to
the 360 family.

On 2023-09-09 03:07, Peter Flass wrote:
> I wasn’t aware of the incompatibilities among various PDP-11 models, but
> the -10s seemed to have areas of incompatibility also. I believe IBM was
> the first to define an “architecture” independent of any particular
> implementation, and then make sure (nearly) all S/360 models conformed to
> it.

The incompatibilities between PDP-11 models mostly came about because
the architecture wasn't really formally defined, but was a lot of
general understanding and "see how the previous implementation did it".
However, in some cases, some slight differences occurred because for
various reasons it was easier/better for the implementors to have a
slightly different behavior, and the architecture didn't have a proper
definition, so it could be said to be wrong.

It's mostly somewhat odd/unused sequences that behave differently.

For example:

MOV R0,(R0)+

the question is, the R0 that is written, is it the value before or after
the increment? Undefined. Different models do it differently.
But this is not a sequence you'd normally be using in your code.

Some instructions might also affect the processor status flags
differently. SWAB affecting the V (overflow) flag, for example.

And of course, the architecture was extended a bit, causing some
additional incompatibilities. Not all PDP-11s have the RTT instruction,
for example.

Because of experiences with the PDP-11, DEC did do a very formal
definition for things on the VAX, to avoid something similar. There are
still a few differences on some VAX CPUs, but I think they probably
classify as bugs.

Johnny

According to Johnny Billquist <bqt@softjar.se>:
>On 2023-09-06 17:49, Joe Pfeiffer wrote:
>> Johnny Billquist <bqt@softjar.se> writes:
>>
>>> On 2023-09-04 13:02, Thomas Koenig wrote:
>>>
>>> The PDP-11 (at least some models) have the exact same behavior with
>>> the registers. The CPU registers do exist in memory space, and you can
>>> run code in them.
>>
>> I don't remember ever coming across this -- which models?
>
>I won't dare trying to list them all. I know that the 11/70 have it,
>which implies that the 11/45, 11/50 and 11/55 also do.

I did a lot of programming on an an 11/45 and I can assure you the
registers were addressable as memory, at least not in any normal way.

>General register set 0 is at 17777700 to 17777707. General register set
>1 is at 17777710 to 17777717.

That was for debugging. It wasn't useful in normal code.

--
Regards,
John Levine, johnl@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly

According to John Levine <johnl@taugh.com>:
>According to Johnny Billquist <bqt@softjar.se>:
>>On 2023-09-06 17:49, Joe Pfeiffer wrote:
>>> Johnny Billquist <bqt@softjar.se> writes:
>>>
>>>> On 2023-09-04 13:02, Thomas Koenig wrote:
>>>>
>>>> The PDP-11 (at least some models) have the exact same behavior with
>>>> the registers. The CPU registers do exist in memory space, and you can
>>>> run code in them.
>>>
>>> I don't remember ever coming across this -- which models?
>>
>>I won't dare trying to list them all. I know that the 11/70 have it,
>>which implies that the 11/45, 11/50 and 11/55 also do.
>
>I did a lot of programming on an an 11/45 and I can assure you the
>registers were addressable as memory, at least not in any normal way.

sigh. were NOT addressable ...
>
>>General register set 0 is at 17777700 to 17777707. General register set
>>1 is at 17777710 to 17777717.
>
>That was for debugging. It wasn't useful in normal code.
>
>--
>Regards,
>John Levine, johnl@taugh.com, Primary Perpetrator of "The Internet for Dummies",
>Please consider the environment before reading this e-mail. https://jl.ly

--
Regards,
John Levine, johnl@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly

According to Thomas Koenig <tkoenig@netcologne.de>:
>John Levine <johnl@taugh.com> schrieb:
>
>> The 360 was such a great success that we now often forget how
>> revolutionary it was. It was not only the first architecture intended
>> from the outset to have multiple implmementations, but it was also the
>> first one with 8 bit bytes and the kind of byte addressing that is now
>> used everywhere, and the first popular machine with a large regular
>> set of registers.
>
>The PDP-6 had something close to 16 registers in its lowest 16
>words of memory, but I guess it is possible to argue that it
>wasn't very popular ...

I actually programmed a PDP-6 when I was in high school.

The first 16 memory locations were the registers. On the PDP-6 and
KA-10, transistor registers were optional, otherwise stored in the
first 16 locations of core, but everyone bought the fast registers so
they became standard on the KI-10.

The PDP-6 was a technical triumph but a commercial failure. They
used large boards with unreliable connectors making the machine
flaky. DEC only made 20 of them, and cancelled the product. It's
not entirely clear to me why they gave the -10 another try but it
was clearly a good move.

S/360 and the PDP-6 were both announced in 1964, so they obviously
both had been designed some time before, as far as I know without
either having knowledge of the other. The first 360s were shipped in
1965, so DEC probably shipped a PDP-6 before IBM shipped a 360, but I
would say they were simultaneous, and the -6 definitely was not
popular, even though it was well loved by its friends.

--
Regards,
John Levine, johnl@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly

Peter Flass <peter_flass@yahoo.com> writes:

> I wasn't aware of the incompatibilities among various PDP-11 models, but the
> -10s seemed to have areas of incompatibility also. I believe IBM was the
> first to define an "architecture�" independent of any particular
> implementation, and then make sure (nearly) all S/360 models conformed to it.

Other than the addition of extended addressing to the KL-10 and KS-10, what
did you have in mind for the PDP-10 systems? Asking for a friend... ;->

--
Rich Alderson news@alderson.users.panix.com
Audendum est, et veritas investiganda; quam etiamsi non assequamur,
omnino tamen proprius, quam nunc sumus, ad eam perveniemus.
--Galen

John Levine <johnl@taugh.com> writes:

> According to Thomas Koenig <tkoenig@netcologne.de>:
>> John Levine <johnl@taugh.com> schrieb:

>>> The 360 was such a great success that we now often forget how revolutionary
>>> it was. It was not only the first architecture intended from the outset to
>>> have multiple implmementations, but it was also the first one with 8 bit
>>> bytes and the kind of byte addressing that is now used everywhere, and the
>>> first popular machine with a large regular set of registers.

>> The PDP-6 had something close to 16 registers in its lowest 16 words of
>> memory, but I guess it is possible to argue that it wasn't very popular ...

> I actually programmed a PDP-6 when I was in high school.

> The first 16 memory locations were the registers. On the PDP-6 and KA-10,
> transistor registers were optional, otherwise stored in the first 16
> locations of core, but everyone bought the fast registers so they became
> standard on the KI-10.

> The PDP-6 was a technical triumph but a commercial failure. They used large
> boards with unreliable connectors making the machine flaky. DEC only made 20
> of them, and cancelled the product. It's not entirely clear to me why they
> gave the -10 another try but it was clearly a good move.

The PDP-6 was a technical triumph, meaning that those customers who purchased a
PPD-6 were very happy with the capabilities of the system even if they were not
particularly happy with the implementation (which was an expansion on the
System Module(TM) technology used successfully in the PDP-1, PDP-4, and PDP-5).

The PDP-10 was designed using the new technology introduced with the PDP-7, the
FlipChip(TM), and used to good effect in the PDP-8 and PDP-9. The 36 bit
architecture redesign was a skunkworks project, hidden from Ken Olsen until it
was ready to go; the initial product line included three models (the 10/10,
10/20, and 10/30) which were nominally single user systems, to make KO happy,
as well as a nonswapping (10/40) and a swapping (10/50) multiuser model.

It is reported that someone did order a 10/30.[1]

> S/360 and the PDP-6 were both announced in 1964, so they obviously both had
> been designed some time before, as far as I know without either having
> knowledge of the other. The first 360s were shipped in 1965, so DEC probably
> shipped a PDP-6 before IBM shipped a 360, but I would say they were
> simultaneous, and the -6 definitely was not popular, even though it was well
> loved by its friends.

The System/360 family were announced in April, 1964, with first customer ship
in October, 1965.

The PDP-6 was announced three weeks before, in March, 1964, with first customer
ship in June, 1964.

A lot less vapor in the PDP-6 than in the S/360, don't you think?

[1] I'd love a PDP-10/30: 32KW memory, paper tape and DECtape, Teletype console.

--
Rich Alderson news@alderson.users.panix.com
Audendum est, et veritas investiganda; quam etiamsi non assequamur,
omnino tamen proprius, quam nunc sumus, ad eam perveniemus.
--Galen

John Levine <johnl@taugh.com> writes:
> S/360 and the PDP-6 were both announced in 1964, so they obviously
> both had been designed some time before, as far as I know without
> either having knowledge of the other. The first 360s were shipped in
> 1965, so DEC probably shipped a PDP-6 before IBM shipped a 360, but I
> would say they were simultaneous, and the -6 definitely was not
> popular, even though it was well loved by its friends.

one of the co-workers (at science center) told story that in the gov/IBM
trial ... that BUNCH members testified that by 1959 all realized that
(because of software costs), all realized that compatible architecture
was needed across the product lines ... but IBM was only one with
executives that managed to enforce compatibility (also required
description that all could follow).

account of the end of the ACS/360 (ACS started out incompatibility, but
Amdahl managed to carry the day for compatibility), executives shut it
down because they were afraid it would advance the state-of-the-art too
fast and would loose control of the market
https://people.cs.clemson.edu/~mark/acs_end.html
Amdahl leaves IBM shortly later.

Early 70s, IBM has the "Future System" project (as countermeasure to
clone mainframe i/o controllers), completely different and going to
completely replace 370. Internal politics were shutting down 370 efforts
(claim is the lack of new 370 during the FS period, is credited with
giving 370 clone makers their market foothold, aka attempting failed
countermeasure to clone controllers enabling rise ofclone systems).

Amdahl gave talk in large MIT auditorium shortly after forming his
company. Somebody in the audience asked him what justification for his
company did he use with investors. He said that there was enough
customer 360 software, that even if IBM was going to completely walk
away from 360 ... it was sufficient to keep him in business through the
end of the century (sort of implying he knew about "FS", but in later
years he claimed he knew nothing about FS).

When FS finally implodes, there was mad rush to get stuff back into 370
product pipelines ... including kicking off the quick&dirty 3033&3081
projects in parallel
http://www.jfsowa.com/computer/memo125.htm
https://en.wikipedia.org/wiki/IBM_Future_Systems_project

trivia: decade ago I was asked (in newsgroups) if I could track down the IBM
decision to add virtual memory to all 370s and found staff to executive
making the decision, basically (OS/360) MVT storage management was so
bad that regions frequently had to be specified four times larger than
used, resulting in typical 1mbyte 370/165 only being able to run four
regions concurrently, insufficient to keep processor busy and
justified. Mapping MVT to 16mbyte virtual memory, allowed increasing
concurrently running regions by a factor of four times with little or
no paing (initially MVT->VS2 was little different than running MVT
in CP67 16mbyte virtual machine). Pieces of that email exchange in this
archived (11mar2011 afc) post
http://www.garlic.com/~lynn/2011d.html#73

trivia2: the 360 (& then 370) architecture manual was moved to CMS
SCRIPT (redone from CTSS RUNOFF), command line option either generated
the principles of operation subset or the full architecture manual (with
engineering notes, justifications, alternative implementations for
different models, etc).
http://www.bitsavers.org/pdf/ibm/360/princOps/
http://www.bitsavers.org/pdf/ibm/370/princOps/

trivia3: 370/165 engineers complained that if they had to do the full
370 virtual memory architecture, it would delay virtual memory announce
by six months. Eventually decision was just to do the 165 subset, and
other models (and software) having already done the full architecture
had to drop back to the 165 subset.

other discussion in this (linkedin) post starting with Learson
attempting to block the bureaucrats, careerists, and MBAs destroying the
watson legacy (but failed) ... two decades later, IBM has one of the
largest losses in US company history and was being re-orged into the 13
"baby blues" in preparation for breaking up the company
https://www.linkedin.com/pulse/john-boyd-ibm-wild-ducks-lynn-wheeler/

--
virtualization experience starting Jan1968, online at home since Mar1970

Rich Alderson <news@alderson.users.panix.com> wrote:
> Peter Flass <peter_flass@yahoo.com> writes:
>
>> I wasn't aware of the incompatibilities among various PDP-11 models, but the
>> -10s seemed to have areas of incompatibility also. I believe IBM was the
>> first to define an "architectureв" independent of any particular
>> implementation, and then make sure (nearly) all S/360 models conformed to it.
>
> Other than the addition of extended addressing to the KL-10 and KS-10, what
> did you have in mind for the PDP-10 systems? Asking for a friend... ;->
>

I don’t have any specific knowledge, other than Barb’s postings about the
travails of the OS guys trying to support new hardware. (mostly
peripherals, but some CPU considerations, I think)

--
Pete

On 2023-09-10 00:24, Rich Alderson wrote:
> Peter Flass <peter_flass@yahoo.com> writes:
>
>> I wasn't aware of the incompatibilities among various PDP-11 models, but the
>> -10s seemed to have areas of incompatibility also. I believe IBM was the
>> first to define an "architectureā" independent of any particular
>> implementation, and then make sure (nearly) all S/360 models conformed to it.
>
> Other than the addition of extended addressing to the KL-10 and KS-10, what
> did you have in mind for the PDP-10 systems? Asking for a friend... ;->

Was byte instructions always in there?
Or was that something that changed just between the -6 and -10?

Obviously, for OSes, there were differences, but that was mainly on I/O
and pager, and weren't anything about instructions as such.

Johnny

On 2023-09-09 22:41, John Levine wrote:
> According to John Levine <johnl@taugh.com>:
>> According to Johnny Billquist <bqt@softjar.se>:
>>> On 2023-09-06 17:49, Joe Pfeiffer wrote:
>>>> Johnny Billquist <bqt@softjar.se> writes:
>>>>
>>>>> On 2023-09-04 13:02, Thomas Koenig wrote:
>>>>>
>>>>> The PDP-11 (at least some models) have the exact same behavior with
>>>>> the registers. The CPU registers do exist in memory space, and you can
>>>>> run code in them.
>>>>
>>>> I don't remember ever coming across this -- which models?
>>>
>>> I won't dare trying to list them all. I know that the 11/70 have it,
>>> which implies that the 11/45, 11/50 and 11/55 also do.
>>
>> I did a lot of programming on an an 11/45 and I can assure you the
>> registers were addressable as memory, at least not in any normal way.
>
> sigh. were NOT addressable ...

I was reading up on some other things, and came across that for the
KB11, they registers are only accessible on those addresses on the front
panel, but not from the CPU.

There are, however, some CPUs where they were also accessible from the
CPU. There are so many variations on the PDP-11...

Johnny

According to Rich Alderson <news@alderson.users.panix.com>:
>The PDP-10 was designed using the new technology introduced with the PDP-7, the
>FlipChip(TM), and used to good effect in the PDP-8 and PDP-9. The 36 bit
>architecture redesign was a skunkworks project, hidden from Ken Olsen until it
>was ready to go; the initial product line included three models (the 10/10,
>10/20, and 10/30) which were nominally single user systems, to make KO happy,
>as well as a nonswapping (10/40) and a swapping (10/50) multiuser model.
>
>It is reported that someone did order a 10/30.[1]

I briefly used a PDP-10 that was used to monitor some kind of high
energy physics experiments at Princeton. I'd think that for some kinds
of realtime stuff it'd make sense, large word size, hardware floating
point, fast interrupts, and a simple hardware interface.

>The System/360 family were announced in April, 1964, with first customer ship
>in October, 1965.
>
>The PDP-6 was announced three weeks before, in March, 1964, with first customer
>ship in June, 1964.
>
>A lot less vapor in the PDP-6 than in the S/360, don't you think?

Not really comparable, the PDP-6 announcement was one machine, S/360
was six, of which they shipped four in 1965. The 360/40 shipped in
April 1965. IBM certainly preannounced to try and keep customers from
jumping ship but the computers were real.
--
Regards,
John Levine, johnl@taugh.com, Primary Perpetrator of "The Internet for Dummies",
Please consider the environment before reading this e-mail. https://jl.ly

Johnny Billquist wrote:
> On 2023-09-10 00:24, Rich Alderson wrote:
> > Other than the addition of extended addressing to the KL-10 and KS-10, what
> > did you have in mind for the PDP-10 systems? Asking for a friend... ;->
> Was byte instructions always in there?
> Or was that something that changed just between the -6 and -10?

Yes, they were theresince the PDP-6. On the KA10 they were "optional".

There were some minor changes between the PDP-6 and the KA10. They are easily avoidable, but strictly speaking, they were not 100% compatible. The KI10 added a few instructions, but was otherwise backwards compatible. The KL10 added a bunch of new instructions. The KS10 kept the same user mode instruction set.

On 2023-09-10 08:07, Lars Brinkhoff wrote:
> Johnny Billquist wrote:
>> On 2023-09-10 00:24, Rich Alderson wrote:
>>> Other than the addition of extended addressing to the KL-10 and KS-10, what
>>> did you have in mind for the PDP-10 systems? Asking for a friend... ;->
>> Was byte instructions always in there?
>> Or was that something that changed just between the -6 and -10?
>
> Yes, they were theresince the PDP-6. On the KA10 they were "optional".
>
> There were some minor changes between the PDP-6 and the KA10. They are easily avoidable, but strictly speaking, they were not 100% compatible. The KI10 added a few instructions, but was otherwise backwards compatible. The KL10 added a bunch of new instructions. The KS10 kept the same user mode instruction set.

So there are some incompatibilities between PDP-10 models. Not as many
as for the PDP-11, and it's more in the line of added instructions. But
it still means differences exist. Which a program could even use to
figure out what model of CPU it is running on.

Johnny