https://priorart.ip.com/IPCOM/000113671

Peripheral Component Interconnect Daughter Card Configuration Disclosed
is a means for addressing a daughter card on a Peripheral Component
Interconnect (PCI) local bus from a system bus during the configuration
process occurring during system initialization, when different
configuration spaces need to be supported in spite of limitations to the
Programmable Option Select (POS) registers supported supported by the
Micro Channel* bus for this purpose.

As shown in Fig. 1, I/O adapter circuits are placed on an I/O adapter
card 10, such as a graphics adapter card, which is connected to the
processor 12 of a computing system by means of a system bus 14. Card 10
may be an ISA card or a Micro Channel card, depending on the nature of
system bus 14, which may be either an ISA bus or a Micro Channel bus.
(In this disclosure, the system bus is considered to be, for example, a
Micro Channel bus). A daughter card 16 is attached to adapter card 10,
being connected to I/O controller circuit 18 by means of a local bus 20,
designated the PCI bus. In this way, the functions supported by the
graphics adapter circuits can be changed by changing the daugheter card
16, supporting, for example, different types of multi-media functions.
Daughter card 16 may alternately be attached to a planar, or system
board (not shown) including graphics adapter circuits and providing the
PCI bus.

The Programmable Option Select (POS) feature of the Micro Channel bus
provides a means for determining and storing the configuration of
adapter cards installed on the system bus. Each different type of
adapter card has its own identifying number, which is stored in the
firmware of the card. These identification numbers are encoded as four
digits and stored as two bytes of data. This information is stored in
battery-powered CMOS memory and in special disk files. During
initialization, a comparison is made between stored configuration
information and the cards actually installed, to ensure the integrity of
the stored configuration information [*].

The PCI architecture allows for 256 bytes of configuration data, having
assignments as indicated in Fig. 2, while the Micro Channel architecture
supports only eight POS registers. During the address phase of the
configuration cycle for the PCI bus, the eight least-significant AD
lines address the 256-byte configuaration space, while the
least-signficant three address lines of the Micro Channel bus address
the Micro Channel POS registers. Each PCI slave uses the Initialization
Device Select (IDSEL) line to determine whether it has been selected
during a configuration sequence. The Micro Channel uses a CDSETUP (Card
Setup) line to signify that the Micro Channel is doing a configuration
sequence, in which the slave receiveing the CDSETUP signal has been
selected.

Thus, during a PCI configuration cycle, it is necessary to access
individual PCI daughter card devices and to address individual 256-byte
configuration spaces. To make this possible, memory regi...

This is just a copy of what's in the US Patent document for the MCA to PCI bridge chip.

Also Russell Padgett appears retired and gone from IBM. Linked in Profile inactive and inside IBM he's not in the system.