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devel / comp.arch.fpga / Calculation of throughput of sub-block in digital design (I)

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o Calculation of throughput of sub-block in digital design (I)Hassan Iqbal

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Calculation of throughput of sub-block in digital design (I)

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Subject: Calculation of throughput of sub-block in digital design (I)
From: matrixofdynamism@googlemail.com (Hassan Iqbal)
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 by: Hassan Iqbal - Sun, 20 Feb 2022 22:18 UTC

I am trying to understand the correct way to calculate throughput of a digital hardware design block that forms part of a bigger system.

Here are the few scenarios:
1. DUT takes 10 clock cycles to generate 20 bit output, then another 10 clock cycles to generate the next 20 bit output.
-> The maximum throughput is 20 bits per 10 clock cycles = 2 bits/cycle

2. DUT takes 10 clock cycles to generate the first 20 bit output, then (being pipelined) it generates a new 20 bit output ever cycle
-> The maximum throughput is 20 bits per 1 clock cycles = 20 bits/cycle

Is this correct or do I have to involve clock frequency to calculate the throughput as well?

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