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devel / comp.arch.fpga / Re: VHDL2019 Webinars

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* Re: VHDL2019 WebinarsW TX
`- Re: VHDL2019 WebinarsHT-Lab

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Re: VHDL2019 Webinars

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Subject: Re: VHDL2019 Webinars
From: wtxwtx@gmail.com (W TX)
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 by: W TX - Tue, 4 May 2021 15:07 UTC

On Sunday, May 2, 2021 at 8:36:36 AM UTC-7, Piotr Wyderski wrote:
> Hi Hans,
> > I assume you are using Vivado's simulator?
> Actually, at the moment it is Lattice Diamond and Lattice Radiant, as
> the FPGA is used mostly for its high-speed LVDS capabilities.
> > in that case yes support is not that great but it is the price you pay for free.
> I must admit that I do not quite follow this argument. In the software
> world I can get both GCC and Clang entirely for free with an almost full
> set of C++ features, often years before the new standard is accepted. I
> have no idea why it should not be the same way with EDA tools. And the
> tools are not free, I have already paid for them buying the chips. This
> is not something I would like to spend too much time on, though; voting
> with my feet is usually the best solution.
> > Unfortunately everybody is so busy producing code that they forget that
> > new language constructs can really help their coding effort and reduce
> > bugs.
> I wanted to use the new language constructs, but then the tools refused
> to interpret them. Writing something that is recognisable by ModelSim,
> Synplify and the Lattice in-house compiler at the same time is a kind of
> an art. I had a similar experience with Quartus before.
> > The same will apply to VHDL2019, there will be language features that
> > everybody will use.
> Not necessarily everybody. I got really tired with the hopelessly
> obsolete HDL support and stared generating more and more HDL files from
> Python scripts, especially when heavy generic support is required. I
> believe I will further pursue this path rather than retract from it.
> It simply works and I no longer need to guess what subset of the newer
> standard was elected for implementation by throwing darts in the
> marketing department of a particular vendor. The output is VHDL93 and if
> something doesn't work, it doesn't work on my end -- I can add arbitrary
> amount of Python preprocessing to fix that.
> > Watch the webinar, see which features you like then log an enhancement
> > request with your simulator supplier, it is worth the effort!
> Last time I did that the supplier asked me how many devices I was
> planning to purchase and what was the purpose of the product. I couldn't
> find any logical connection between the question I asked and the
> response I got, so I decided that any further contact would be pointless.
>
> Best regards, Piotr
I like to let Jim transfer all Webinars to Youtube so that everyone at any time at any place can view his presentation.

I like many Webinars presentations, but mostly I miss all interesting subjects, because it provides the presentation at a fixed time, and one cannot review it again later.

Weng

Re: VHDL2019 Webinars

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Reply-To: hans64@htminuslab.com
Subject: Re: VHDL2019 Webinars
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From: hans64@htminuslab.com (HT-Lab)
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 by: HT-Lab - Sat, 8 May 2021 17:06 UTC

On 04/05/2021 16:07, W TX wrote:
> On Sunday, May 2, 2021 at 8:36:36 AM UTC-7, Piotr Wyderski wrote:
...
>>
>> Best regards, Piotr
> I like to let Jim transfer all Webinars to Youtube so that everyone at any time at any place can view his presentation.
>
> I like many Webinars presentations, but mostly I miss all interesting subjects, because it provides the presentation at a fixed time, and one cannot review it again later.
>
> Weng

Hi Weng,

Not sure which webinars you signed up for but I nearly always get a link
to watch the webinar again. The last 3 where Doulos, Microchip and
DVclub and they all send me a link to watch it again.

I am not sure youtube is any better platform given the excessive adverts
I am getting lately (might be because I also click skip ads as quick as
possible.....)

Hans
www.ht-lab.com

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