The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.

e.g. apps/color_toy.py:

include('FPGAburn/appload.py') # must be on the first line

# play with LD0 color

ja(fwd('init'))

lbl('app_msg'); ascii('\r\npress BTN0 to reset')

# color intensities
lbl('red'); data([0])
lbl('green'); data([0])
lbl('blue'); data([0])

# commands

lbl('ir') # char -> # increment red
drop(); lld(red); inc(); lst(red); ret()

lbl('dr') # char -> # decrement red
drop(); lld(red); dec(); lst(red); ret()

lbl('ig') # char -> # increment green
drop(); lld(green); inc(); lst(green); ret()

lbl('dg') # char -> # decrement green
drop(); lld(green); dec(); lst(green); ret()

lbl('ib') # char -> # increment blue
drop(); lld(blue); inc(); lst(blue); ret()

lbl('db') # char -> # decrement blue
drop(); lld(blue); dec(); lst(blue); ret()

lbl('command') # -> # execute a recognized command
lld(arx_rdy)
_if()
lld(uart); dup(); cp(tx) # -> char # echo
dup(); lbxor(ord('R')); jz(ir)
dup(); lbxor(ord('r')); jz(dr)
dup(); lbxor(ord('G')); jz(ig)
dup(); lbxor(ord('g')); jz(dg)
dup(); lbxor(ord('B')); jz(ib)
dup(); lbxor(ord('b')); jz(db)
drop() # none of the above
_then()
ret()

lbl('init')
lit(app_msg); cp(tx_ascii)
_begin()
cp(command)
lld(red); lst(pwm1)
lld(green); lst(pwm2)
lld(blue); lst(pwm3)
_again()

lbl('app_end') # must be on the last line

BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
A link to Bugs18bis.zip is in the downloads section.

Cheers - Myron Plichota

On Wednesday, November 30, 2022 at 7:55:49 AM UTC-5, Myron Plichota wrote:
> The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
>
> e.g. apps/color_toy.py:
>
> include('FPGAburn/appload.py') # must be on the first line
>
> # play with LD0 color
>
> ja(fwd('init'))
>
> lbl('app_msg'); ascii('\r\npress BTN0 to reset')
>
> # color intensities
> lbl('red'); data([0])
> lbl('green'); data([0])
> lbl('blue'); data([0])
>
> # commands
>
> lbl('ir') # char -> # increment red
> drop(); lld(red); inc(); lst(red); ret()
>
> lbl('dr') # char -> # decrement red
> drop(); lld(red); dec(); lst(red); ret()
>
> lbl('ig') # char -> # increment green
> drop(); lld(green); inc(); lst(green); ret()
>
> lbl('dg') # char -> # decrement green
> drop(); lld(green); dec(); lst(green); ret()
>
> lbl('ib') # char -> # increment blue
> drop(); lld(blue); inc(); lst(blue); ret()
>
> lbl('db') # char -> # decrement blue
> drop(); lld(blue); dec(); lst(blue); ret()
>
> lbl('command') # -> # execute a recognized command
> lld(arx_rdy)
> _if()
> lld(uart); dup(); cp(tx) # -> char # echo
> dup(); lbxor(ord('R')); jz(ir)
> dup(); lbxor(ord('r')); jz(dr)
> dup(); lbxor(ord('G')); jz(ig)
> dup(); lbxor(ord('g')); jz(dg)
> dup(); lbxor(ord('B')); jz(ib)
> dup(); lbxor(ord('b')); jz(db)
> drop() # none of the above
> _then()
> ret()
>
> lbl('init')
> lit(app_msg); cp(tx_ascii)
> _begin()
> cp(command)
> lld(red); lst(pwm1)
> lld(green); lst(pwm2)
> lld(blue); lst(pwm3)
> _again()
>
> lbl('app_end') # must be on the last line
>
> BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> A link to Bugs18bis.zip is in the downloads section.
>
> Cheers - Myron Plichota
It's a pity that the indentation was screwed up by the new post tool :(

On 2022-11-30 13:00, Myron Plichota wrote:
> On Wednesday, November 30, 2022 at 7:55:49 AM UTC-5, Myron Plichota wrote:
>>
>> e.g. apps/color_toy.py:
>>
[...]

> It's a pity that the indentation was screwed up by the new post tool :(

It's a problem in the Google Groups reader only.

All the indentations are kept in your message when it's accessed via NNTP.

For example, see:
http://al.howardknight.net/?ID=166988358200
https://news.novabbs.com/programming/article-flat.php?id=21463&group=comp.lang.forth#21463

--
Ruvim

On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
>
> e.g. apps/color_toy.py:
>
> include('FPGAburn/appload.py') # must be on the first line
>
> # play with LD0 color
>
> ja(fwd('init'))
>
> lbl('app_msg'); ascii('\r\npress BTN0 to reset')
>
> # color intensities
> lbl('red'); data([0])
> lbl('green'); data([0])
> lbl('blue'); data([0])
>
> # commands
>
> lbl('ir') # char -> # increment red
> drop(); lld(red); inc(); lst(red); ret()
>
> lbl('dr') # char -> # decrement red
> drop(); lld(red); dec(); lst(red); ret()
>
> lbl('ig') # char -> # increment green
> drop(); lld(green); inc(); lst(green); ret()
>
> lbl('dg') # char -> # decrement green
> drop(); lld(green); dec(); lst(green); ret()
>
> lbl('ib') # char -> # increment blue
> drop(); lld(blue); inc(); lst(blue); ret()
>
> lbl('db') # char -> # decrement blue
> drop(); lld(blue); dec(); lst(blue); ret()
>
> lbl('command') # -> # execute a recognized command
> lld(arx_rdy)
> _if()
> lld(uart); dup(); cp(tx) # -> char # echo
> dup(); lbxor(ord('R')); jz(ir)
> dup(); lbxor(ord('r')); jz(dr)
> dup(); lbxor(ord('G')); jz(ig)
> dup(); lbxor(ord('g')); jz(dg)
> dup(); lbxor(ord('B')); jz(ib)
> dup(); lbxor(ord('b')); jz(db)
> drop() # none of the above
> _then()
> ret()
>
> lbl('init')
> lit(app_msg); cp(tx_ascii)
> _begin()
> cp(command)
> lld(red); lst(pwm1)
> lld(green); lst(pwm2)
> lld(blue); lst(pwm3)
> _again()
>
> lbl('app_end') # must be on the last line
>
> BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> A link to Bugs18bis.zip is in the downloads section.
>
> Cheers - Myron Plichota

The number of people who own such a board is probably rather small.
And cost/availability might be an issue for many who want to give it a go.

I wonder if the NANDLAND Board / Lattice based could be a target for your software.
This would probably cover as well the related board from Lattice.
https://nandland.com/the-go-board/ has a lot of related documentation to get started.

Nandland board $65,
https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment

On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> >
> > e.g. apps/color_toy.py:
> >
> > include('FPGAburn/appload.py') # must be on the first line
> >
> > # play with LD0 color
> >
> > ja(fwd('init'))
> >
> > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> >
> > # color intensities
> > lbl('red'); data([0])
> > lbl('green'); data([0])
> > lbl('blue'); data([0])
> >
> > # commands
> >
> > lbl('ir') # char -> # increment red
> > drop(); lld(red); inc(); lst(red); ret()
> >
> > lbl('dr') # char -> # decrement red
> > drop(); lld(red); dec(); lst(red); ret()
> >
> > lbl('ig') # char -> # increment green
> > drop(); lld(green); inc(); lst(green); ret()
> >
> > lbl('dg') # char -> # decrement green
> > drop(); lld(green); dec(); lst(green); ret()
> >
> > lbl('ib') # char -> # increment blue
> > drop(); lld(blue); inc(); lst(blue); ret()
> >
> > lbl('db') # char -> # decrement blue
> > drop(); lld(blue); dec(); lst(blue); ret()
> >
> > lbl('command') # -> # execute a recognized command
> > lld(arx_rdy)
> > _if()
> > lld(uart); dup(); cp(tx) # -> char # echo
> > dup(); lbxor(ord('R')); jz(ir)
> > dup(); lbxor(ord('r')); jz(dr)
> > dup(); lbxor(ord('G')); jz(ig)
> > dup(); lbxor(ord('g')); jz(dg)
> > dup(); lbxor(ord('B')); jz(ib)
> > dup(); lbxor(ord('b')); jz(db)
> > drop() # none of the above
> > _then()
> > ret()
> >
> > lbl('init')
> > lit(app_msg); cp(tx_ascii)
> > _begin()
> > cp(command)
> > lld(red); lst(pwm1)
> > lld(green); lst(pwm2)
> > lld(blue); lst(pwm3)
> > _again()
> >
> > lbl('app_end') # must be on the last line
> >
> > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > A link to Bugs18bis.zip is in the downloads section.
> >
> > Cheers - Myron Plichota
> The number of people who own such a board is probably rather small.
> And cost/availability might be an issue for many who want to give it a go.
>
> I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> This would probably cover as well the related board from Lattice.
> https://nandland.com/the-go-board/ has a lot of related documentation to get started.
>
> Nandland board $65,
> https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment

FPGA board prices have gone way op over the last few years.
If you are a FPGA beginner and a student and want to avoid using a plug board,
the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.

On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > >
> > > e.g. apps/color_toy.py:
> > >
> > > include('FPGAburn/appload.py') # must be on the first line
> > >
> > > # play with LD0 color
> > >
> > > ja(fwd('init'))
> > >
> > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > >
> > > # color intensities
> > > lbl('red'); data([0])
> > > lbl('green'); data([0])
> > > lbl('blue'); data([0])
> > >
> > > # commands
> > >
> > > lbl('ir') # char -> # increment red
> > > drop(); lld(red); inc(); lst(red); ret()
> > >
> > > lbl('dr') # char -> # decrement red
> > > drop(); lld(red); dec(); lst(red); ret()
> > >
> > > lbl('ig') # char -> # increment green
> > > drop(); lld(green); inc(); lst(green); ret()
> > >
> > > lbl('dg') # char -> # decrement green
> > > drop(); lld(green); dec(); lst(green); ret()
> > >
> > > lbl('ib') # char -> # increment blue
> > > drop(); lld(blue); inc(); lst(blue); ret()
> > >
> > > lbl('db') # char -> # decrement blue
> > > drop(); lld(blue); dec(); lst(blue); ret()
> > >
> > > lbl('command') # -> # execute a recognized command
> > > lld(arx_rdy)
> > > _if()
> > > lld(uart); dup(); cp(tx) # -> char # echo
> > > dup(); lbxor(ord('R')); jz(ir)
> > > dup(); lbxor(ord('r')); jz(dr)
> > > dup(); lbxor(ord('G')); jz(ig)
> > > dup(); lbxor(ord('g')); jz(dg)
> > > dup(); lbxor(ord('B')); jz(ib)
> > > dup(); lbxor(ord('b')); jz(db)
> > > drop() # none of the above
> > > _then()
> > > ret()
> > >
> > > lbl('init')
> > > lit(app_msg); cp(tx_ascii)
> > > _begin()
> > > cp(command)
> > > lld(red); lst(pwm1)
> > > lld(green); lst(pwm2)
> > > lld(blue); lst(pwm3)
> > > _again()
> > >
> > > lbl('app_end') # must be on the last line
> > >
> > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > A link to Bugs18bis.zip is in the downloads section.
> > >
> > > Cheers - Myron Plichota
> > The number of people who own such a board is probably rather small.
> > And cost/availability might be an issue for many who want to give it a go.
> >
> > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > This would probably cover as well the related board from Lattice.
> > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> >
> > Nandland board $65,
> > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> FPGA board prices have gone way op over the last few years.
> If you are a FPGA beginner and a student and want to avoid using a plug board,
> the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.

I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
https://shop.pimoroni.com/search?q=fpga%20board
But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
The last time I switched one on, was
to verify the CDP1802 that Steve Teal did
https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
All for the fun of it.

On Saturday, December 3, 2022 at 6:32:00 AM UTC-5, jpit...@gmail.com wrote:
> On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> >
> > e.g. apps/color_toy.py:
> >
> > include('FPGAburn/appload.py') # must be on the first line
> >
> > # play with LD0 color
> >
> > ja(fwd('init'))
> >
> > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> >
> > # color intensities
> > lbl('red'); data([0])
> > lbl('green'); data([0])
> > lbl('blue'); data([0])
> >
> > # commands
> >
> > lbl('ir') # char -> # increment red
> > drop(); lld(red); inc(); lst(red); ret()
> >
> > lbl('dr') # char -> # decrement red
> > drop(); lld(red); dec(); lst(red); ret()
> >
> > lbl('ig') # char -> # increment green
> > drop(); lld(green); inc(); lst(green); ret()
> >
> > lbl('dg') # char -> # decrement green
> > drop(); lld(green); dec(); lst(green); ret()
> >
> > lbl('ib') # char -> # increment blue
> > drop(); lld(blue); inc(); lst(blue); ret()
> >
> > lbl('db') # char -> # decrement blue
> > drop(); lld(blue); dec(); lst(blue); ret()
> >
> > lbl('command') # -> # execute a recognized command
> > lld(arx_rdy)
> > _if()
> > lld(uart); dup(); cp(tx) # -> char # echo
> > dup(); lbxor(ord('R')); jz(ir)
> > dup(); lbxor(ord('r')); jz(dr)
> > dup(); lbxor(ord('G')); jz(ig)
> > dup(); lbxor(ord('g')); jz(dg)
> > dup(); lbxor(ord('B')); jz(ib)
> > dup(); lbxor(ord('b')); jz(db)
> > drop() # none of the above
> > _then()
> > ret()
> >
> > lbl('init')
> > lit(app_msg); cp(tx_ascii)
> > _begin()
> > cp(command)
> > lld(red); lst(pwm1)
> > lld(green); lst(pwm2)
> > lld(blue); lst(pwm3)
> > _again()
> >
> > lbl('app_end') # must be on the last line
> >
> > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > A link to Bugs18bis.zip is in the downloads section.
> >
> > Cheers - Myron Plichota
> The number of people who own such a board is probably rather small.
> And cost/availability might be an issue for many who want to give it a go.
>
> I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> This would probably cover as well the related board from Lattice.
> https://nandland.com/the-go-board/ has a lot of related documentation to get started.
>
> Nandland board $65,
> https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
I have built Lattice iCE40 HX1k and HX8k stack-machine SoCs for the iCEstick and EB85.
HX1k can provide 2Kx18-bits of RAM, 9 of 16 blocks.
HX8k can provide 6Kx18-bits of RAM, 27 of 32 blocks.
iCE40 has no multiplier blocks.
The Go Board IO pinout philosophy is very dedicated.
I have no skin in the game, but I do not recommend this particular board for a Verilog transplant operation.

On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > >
> > > > e.g. apps/color_toy.py:
> > > >
> > > > include('FPGAburn/appload.py') # must be on the first line
> > > >
> > > > # play with LD0 color
> > > >
> > > > ja(fwd('init'))
> > > >
> > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > >
> > > > # color intensities
> > > > lbl('red'); data([0])
> > > > lbl('green'); data([0])
> > > > lbl('blue'); data([0])
> > > >
> > > > # commands
> > > >
> > > > lbl('ir') # char -> # increment red
> > > > drop(); lld(red); inc(); lst(red); ret()
> > > >
> > > > lbl('dr') # char -> # decrement red
> > > > drop(); lld(red); dec(); lst(red); ret()
> > > >
> > > > lbl('ig') # char -> # increment green
> > > > drop(); lld(green); inc(); lst(green); ret()
> > > >
> > > > lbl('dg') # char -> # decrement green
> > > > drop(); lld(green); dec(); lst(green); ret()
> > > >
> > > > lbl('ib') # char -> # increment blue
> > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > >
> > > > lbl('db') # char -> # decrement blue
> > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > >
> > > > lbl('command') # -> # execute a recognized command
> > > > lld(arx_rdy)
> > > > _if()
> > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > dup(); lbxor(ord('R')); jz(ir)
> > > > dup(); lbxor(ord('r')); jz(dr)
> > > > dup(); lbxor(ord('G')); jz(ig)
> > > > dup(); lbxor(ord('g')); jz(dg)
> > > > dup(); lbxor(ord('B')); jz(ib)
> > > > dup(); lbxor(ord('b')); jz(db)
> > > > drop() # none of the above
> > > > _then()
> > > > ret()
> > > >
> > > > lbl('init')
> > > > lit(app_msg); cp(tx_ascii)
> > > > _begin()
> > > > cp(command)
> > > > lld(red); lst(pwm1)
> > > > lld(green); lst(pwm2)
> > > > lld(blue); lst(pwm3)
> > > > _again()
> > > >
> > > > lbl('app_end') # must be on the last line
> > > >
> > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > A link to Bugs18bis.zip is in the downloads section.
> > > >
> > > > Cheers - Myron Plichota
> > > The number of people who own such a board is probably rather small.
> > > And cost/availability might be an issue for many who want to give it a go.
> > >
> > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > This would probably cover as well the related board from Lattice.
> > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > >
> > > Nandland board $65,
> > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > FPGA board prices have gone way op over the last few years.
> > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> https://shop.pimoroni.com/search?q=fpga%20board
> But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> The last time I switched one on, was
> to verify the CDP1802 that Steve Teal did
> https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> All for the fun of it.
CDP1802! I cut my teeth on that axe and began my love/hate relationship with Forth in COSMAC land.

On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > >
> > > > e.g. apps/color_toy.py:
> > > >
> > > > include('FPGAburn/appload.py') # must be on the first line
> > > >
> > > > # play with LD0 color
> > > >
> > > > ja(fwd('init'))
> > > >
> > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > >
> > > > # color intensities
> > > > lbl('red'); data([0])
> > > > lbl('green'); data([0])
> > > > lbl('blue'); data([0])
> > > >
> > > > # commands
> > > >
> > > > lbl('ir') # char -> # increment red
> > > > drop(); lld(red); inc(); lst(red); ret()
> > > >
> > > > lbl('dr') # char -> # decrement red
> > > > drop(); lld(red); dec(); lst(red); ret()
> > > >
> > > > lbl('ig') # char -> # increment green
> > > > drop(); lld(green); inc(); lst(green); ret()
> > > >
> > > > lbl('dg') # char -> # decrement green
> > > > drop(); lld(green); dec(); lst(green); ret()
> > > >
> > > > lbl('ib') # char -> # increment blue
> > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > >
> > > > lbl('db') # char -> # decrement blue
> > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > >
> > > > lbl('command') # -> # execute a recognized command
> > > > lld(arx_rdy)
> > > > _if()
> > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > dup(); lbxor(ord('R')); jz(ir)
> > > > dup(); lbxor(ord('r')); jz(dr)
> > > > dup(); lbxor(ord('G')); jz(ig)
> > > > dup(); lbxor(ord('g')); jz(dg)
> > > > dup(); lbxor(ord('B')); jz(ib)
> > > > dup(); lbxor(ord('b')); jz(db)
> > > > drop() # none of the above
> > > > _then()
> > > > ret()
> > > >
> > > > lbl('init')
> > > > lit(app_msg); cp(tx_ascii)
> > > > _begin()
> > > > cp(command)
> > > > lld(red); lst(pwm1)
> > > > lld(green); lst(pwm2)
> > > > lld(blue); lst(pwm3)
> > > > _again()
> > > >
> > > > lbl('app_end') # must be on the last line
> > > >
> > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > A link to Bugs18bis.zip is in the downloads section.
> > > >
> > > > Cheers - Myron Plichota
> > > The number of people who own such a board is probably rather small.
> > > And cost/availability might be an issue for many who want to give it a go.
> > >
> > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > This would probably cover as well the related board from Lattice.
> > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > >
> > > Nandland board $65,
> > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > FPGA board prices have gone way op over the last few years.
> > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> https://shop.pimoroni.com/search?q=fpga%20board
> But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> The last time I switched one on, was
> to verify the CDP1802 that Steve Teal did
> https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> All for the fun of it.
https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
This has definite transplant potential. It uses the same XC7S25 FPGA.
But:
1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.

The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
I'd be delighted to hear about succesful mutations on other FPGA-based boards.

On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > >
> > > > > e.g. apps/color_toy.py:
> > > > >
> > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > >
> > > > > # play with LD0 color
> > > > >
> > > > > ja(fwd('init'))
> > > > >
> > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > >
> > > > > # color intensities
> > > > > lbl('red'); data([0])
> > > > > lbl('green'); data([0])
> > > > > lbl('blue'); data([0])
> > > > >
> > > > > # commands
> > > > >
> > > > > lbl('ir') # char -> # increment red
> > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > >
> > > > > lbl('dr') # char -> # decrement red
> > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > >
> > > > > lbl('ig') # char -> # increment green
> > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > >
> > > > > lbl('dg') # char -> # decrement green
> > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > >
> > > > > lbl('ib') # char -> # increment blue
> > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > >
> > > > > lbl('db') # char -> # decrement blue
> > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > >
> > > > > lbl('command') # -> # execute a recognized command
> > > > > lld(arx_rdy)
> > > > > _if()
> > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > drop() # none of the above
> > > > > _then()
> > > > > ret()
> > > > >
> > > > > lbl('init')
> > > > > lit(app_msg); cp(tx_ascii)
> > > > > _begin()
> > > > > cp(command)
> > > > > lld(red); lst(pwm1)
> > > > > lld(green); lst(pwm2)
> > > > > lld(blue); lst(pwm3)
> > > > > _again()
> > > > >
> > > > > lbl('app_end') # must be on the last line
> > > > >
> > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > >
> > > > > Cheers - Myron Plichota
> > > > The number of people who own such a board is probably rather small.
> > > > And cost/availability might be an issue for many who want to give it a go.
> > > >
> > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > This would probably cover as well the related board from Lattice.
> > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > >
> > > > Nandland board $65,
> > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > FPGA board prices have gone way op over the last few years.
> > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > https://shop.pimoroni.com/search?q=fpga%20board
> > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > The last time I switched one on, was
> > to verify the CDP1802 that Steve Teal did
> > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > All for the fun of it.
> https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> This has definite transplant potential. It uses the same XC7S25 FPGA.
> But:
> 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
>
> The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> I'd be delighted to hear about succesful mutations on other FPGA-based boards.

There are so many versions on the website, this one might fit better for you
https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/

And regarding 0.1" pitch: I have used this solution in the past:
male headers soldered into the board
female header stuck onlo them
short wires soldered to female header
the other end of the wire soldered onto male header and this stuck into the breadboard.
And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...

On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > >
> > > > > > e.g. apps/color_toy.py:
> > > > > >
> > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > >
> > > > > > # play with LD0 color
> > > > > >
> > > > > > ja(fwd('init'))
> > > > > >
> > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > >
> > > > > > # color intensities
> > > > > > lbl('red'); data([0])
> > > > > > lbl('green'); data([0])
> > > > > > lbl('blue'); data([0])
> > > > > >
> > > > > > # commands
> > > > > >
> > > > > > lbl('ir') # char -> # increment red
> > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > >
> > > > > > lbl('dr') # char -> # decrement red
> > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > >
> > > > > > lbl('ig') # char -> # increment green
> > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > >
> > > > > > lbl('dg') # char -> # decrement green
> > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > >
> > > > > > lbl('ib') # char -> # increment blue
> > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > >
> > > > > > lbl('db') # char -> # decrement blue
> > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > >
> > > > > > lbl('command') # -> # execute a recognized command
> > > > > > lld(arx_rdy)
> > > > > > _if()
> > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > drop() # none of the above
> > > > > > _then()
> > > > > > ret()
> > > > > >
> > > > > > lbl('init')
> > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > _begin()
> > > > > > cp(command)
> > > > > > lld(red); lst(pwm1)
> > > > > > lld(green); lst(pwm2)
> > > > > > lld(blue); lst(pwm3)
> > > > > > _again()
> > > > > >
> > > > > > lbl('app_end') # must be on the last line
> > > > > >
> > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > >
> > > > > > Cheers - Myron Plichota
> > > > > The number of people who own such a board is probably rather small.
> > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > >
> > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > This would probably cover as well the related board from Lattice.
> > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > >
> > > > > Nandland board $65,
> > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > FPGA board prices have gone way op over the last few years.
> > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > https://shop.pimoroni.com/search?q=fpga%20board
> > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > The last time I switched one on, was
> > > to verify the CDP1802 that Steve Teal did
> > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > All for the fun of it.
> > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > But:
> > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> >
> > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> There are so many versions on the website, this one might fit better for you
> https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
>
> And regarding 0.1" pitch: I have used this solution in the past:
> male headers soldered into the board
> female header stuck onlo them
> short wires soldered to female header
> the other end of the wire soldered onto male header and this stuck into the breadboard.
> And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
A quick review of the FPGA datasheet shows problems:
1) block RAM lacks separate read and write clocks in single-port mode
2) there is a maximum of 26Kx18-bits block RAM available
I do not recommend that board.

On Monday, 5 December 2022 at 08:38:14 UTC, Myron Plichota wrote:
> On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > >
> > > > > > > e.g. apps/color_toy.py:
> > > > > > >
> > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > >
> > > > > > > # play with LD0 color
> > > > > > >
> > > > > > > ja(fwd('init'))
> > > > > > >
> > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > >
> > > > > > > # color intensities
> > > > > > > lbl('red'); data([0])
> > > > > > > lbl('green'); data([0])
> > > > > > > lbl('blue'); data([0])
> > > > > > >
> > > > > > > # commands
> > > > > > >
> > > > > > > lbl('ir') # char -> # increment red
> > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > >
> > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > >
> > > > > > > lbl('ig') # char -> # increment green
> > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > >
> > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > >
> > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > >
> > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > >
> > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > lld(arx_rdy)
> > > > > > > _if()
> > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > drop() # none of the above
> > > > > > > _then()
> > > > > > > ret()
> > > > > > >
> > > > > > > lbl('init')
> > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > _begin()
> > > > > > > cp(command)
> > > > > > > lld(red); lst(pwm1)
> > > > > > > lld(green); lst(pwm2)
> > > > > > > lld(blue); lst(pwm3)
> > > > > > > _again()
> > > > > > >
> > > > > > > lbl('app_end') # must be on the last line
> > > > > > >
> > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > >
> > > > > > > Cheers - Myron Plichota
> > > > > > The number of people who own such a board is probably rather small.
> > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > >
> > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > This would probably cover as well the related board from Lattice.
> > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > >
> > > > > > Nandland board $65,
> > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > FPGA board prices have gone way op over the last few years.
> > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > The last time I switched one on, was
> > > > to verify the CDP1802 that Steve Teal did
> > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > All for the fun of it.
> > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > But:
> > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > >
> > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > There are so many versions on the website, this one might fit better for you
> > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> >
> > And regarding 0.1" pitch: I have used this solution in the past:
> > male headers soldered into the board
> > female header stuck onlo them
> > short wires soldered to female header
> > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> A quick review of the FPGA datasheet shows problems:
> 1) block RAM lacks separate read and write clocks in single-port mode
> 2) there is a maximum of 26Kx18-bits block RAM available
> I do not recommend that board.

I think we are looking at this the wrong way around.
I just picked one of the large variety there that seemed to fit nicely
regarding prototyping and breadboard and had USB.
You are the specialist who knows what you want to your applications.

On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
> On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > >
> > > > > > > e.g. apps/color_toy.py:
> > > > > > >
> > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > >
> > > > > > > # play with LD0 color
> > > > > > >
> > > > > > > ja(fwd('init'))
> > > > > > >
> > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > >
> > > > > > > # color intensities
> > > > > > > lbl('red'); data([0])
> > > > > > > lbl('green'); data([0])
> > > > > > > lbl('blue'); data([0])
> > > > > > >
> > > > > > > # commands
> > > > > > >
> > > > > > > lbl('ir') # char -> # increment red
> > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > >
> > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > >
> > > > > > > lbl('ig') # char -> # increment green
> > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > >
> > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > >
> > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > >
> > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > >
> > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > lld(arx_rdy)
> > > > > > > _if()
> > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > drop() # none of the above
> > > > > > > _then()
> > > > > > > ret()
> > > > > > >
> > > > > > > lbl('init')
> > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > _begin()
> > > > > > > cp(command)
> > > > > > > lld(red); lst(pwm1)
> > > > > > > lld(green); lst(pwm2)
> > > > > > > lld(blue); lst(pwm3)
> > > > > > > _again()
> > > > > > >
> > > > > > > lbl('app_end') # must be on the last line
> > > > > > >
> > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > >
> > > > > > > Cheers - Myron Plichota
> > > > > > The number of people who own such a board is probably rather small.
> > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > >
> > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > This would probably cover as well the related board from Lattice.
> > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > >
> > > > > > Nandland board $65,
> > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > FPGA board prices have gone way op over the last few years.
> > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > The last time I switched one on, was
> > > > to verify the CDP1802 that Steve Teal did
> > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > All for the fun of it.
> > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > But:
> > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > >
> > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > There are so many versions on the website, this one might fit better for you
> > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> >
> > And regarding 0.1" pitch: I have used this solution in the past:
> > male headers soldered into the board
> > female header stuck onlo them
> > short wires soldered to female header
> > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> A quick review of the FPGA datasheet shows problems:
> 1) block RAM lacks separate read and write clocks in single-port mode

That would be called "semi-dual port" mode.

> 2) there is a maximum of 26Kx18-bits block RAM available

Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.

> I do not recommend that board.

For what?

If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a serial port.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

On Monday, December 5, 2022 at 12:53:15 PM UTC-5, Lorem Ipsum wrote:
> On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
> > On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> > > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > > >
> > > > > > > > e.g. apps/color_toy.py:
> > > > > > > >
> > > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > > >
> > > > > > > > # play with LD0 color
> > > > > > > >
> > > > > > > > ja(fwd('init'))
> > > > > > > >
> > > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > > >
> > > > > > > > # color intensities
> > > > > > > > lbl('red'); data([0])
> > > > > > > > lbl('green'); data([0])
> > > > > > > > lbl('blue'); data([0])
> > > > > > > >
> > > > > > > > # commands
> > > > > > > >
> > > > > > > > lbl('ir') # char -> # increment red
> > > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > > >
> > > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > > >
> > > > > > > > lbl('ig') # char -> # increment green
> > > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > > >
> > > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > > >
> > > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > > >
> > > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > > >
> > > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > > lld(arx_rdy)
> > > > > > > > _if()
> > > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > > drop() # none of the above
> > > > > > > > _then()
> > > > > > > > ret()
> > > > > > > >
> > > > > > > > lbl('init')
> > > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > > _begin()
> > > > > > > > cp(command)
> > > > > > > > lld(red); lst(pwm1)
> > > > > > > > lld(green); lst(pwm2)
> > > > > > > > lld(blue); lst(pwm3)
> > > > > > > > _again()
> > > > > > > >
> > > > > > > > lbl('app_end') # must be on the last line
> > > > > > > >
> > > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > > >
> > > > > > > > Cheers - Myron Plichota
> > > > > > > The number of people who own such a board is probably rather small.
> > > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > > >
> > > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > > This would probably cover as well the related board from Lattice.
> > > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > > >
> > > > > > > Nandland board $65,
> > > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > > FPGA board prices have gone way op over the last few years.
> > > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > > The last time I switched one on, was
> > > > > to verify the CDP1802 that Steve Teal did
> > > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > > All for the fun of it.
> > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > > But:
> > > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > > >
> > > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > > There are so many versions on the website, this one might fit better for you
> > > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> > >
> > > And regarding 0.1" pitch: I have used this solution in the past:
> > > male headers soldered into the board
> > > female header stuck onlo them
> > > short wires soldered to female header
> > > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> > A quick review of the FPGA datasheet shows problems:
> > 1) block RAM lacks separate read and write clocks in single-port mode
>
> That would be called "semi-dual port" mode.
>
> > 2) there is a maximum of 26Kx18-bits block RAM available
>
> Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
>
> > I do not recommend that board.
>
> For what?
>
> If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it.. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a serial port.

On Monday, December 5, 2022 at 3:51:26 AM UTC-5, jpit...@gmail.com wrote:
> On Monday, 5 December 2022 at 08:38:14 UTC, Myron Plichota wrote:
> > On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> > > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > > >
> > > > > > > > e.g. apps/color_toy.py:
> > > > > > > >
> > > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > > >
> > > > > > > > # play with LD0 color
> > > > > > > >
> > > > > > > > ja(fwd('init'))
> > > > > > > >
> > > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > > >
> > > > > > > > # color intensities
> > > > > > > > lbl('red'); data([0])
> > > > > > > > lbl('green'); data([0])
> > > > > > > > lbl('blue'); data([0])
> > > > > > > >
> > > > > > > > # commands
> > > > > > > >
> > > > > > > > lbl('ir') # char -> # increment red
> > > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > > >
> > > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > > >
> > > > > > > > lbl('ig') # char -> # increment green
> > > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > > >
> > > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > > >
> > > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > > >
> > > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > > >
> > > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > > lld(arx_rdy)
> > > > > > > > _if()
> > > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > > drop() # none of the above
> > > > > > > > _then()
> > > > > > > > ret()
> > > > > > > >
> > > > > > > > lbl('init')
> > > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > > _begin()
> > > > > > > > cp(command)
> > > > > > > > lld(red); lst(pwm1)
> > > > > > > > lld(green); lst(pwm2)
> > > > > > > > lld(blue); lst(pwm3)
> > > > > > > > _again()
> > > > > > > >
> > > > > > > > lbl('app_end') # must be on the last line
> > > > > > > >
> > > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > > >
> > > > > > > > Cheers - Myron Plichota
> > > > > > > The number of people who own such a board is probably rather small.
> > > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > > >
> > > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > > This would probably cover as well the related board from Lattice.
> > > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > > >
> > > > > > > Nandland board $65,
> > > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > > FPGA board prices have gone way op over the last few years.
> > > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > > The last time I switched one on, was
> > > > > to verify the CDP1802 that Steve Teal did
> > > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > > All for the fun of it.
> > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > > But:
> > > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > > >
> > > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > > There are so many versions on the website, this one might fit better for you
> > > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> > >
> > > And regarding 0.1" pitch: I have used this solution in the past:
> > > male headers soldered into the board
> > > female header stuck onlo them
> > > short wires soldered to female header
> > > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> > A quick review of the FPGA datasheet shows problems:
> > 1) block RAM lacks separate read and write clocks in single-port mode
> > 2) there is a maximum of 26Kx18-bits block RAM available
> > I do not recommend that board.
> I think we are looking at this the wrong way around.
> I just picked one of the large variety there that seemed to fit nicely
> regarding prototyping and breadboard and had USB.
> You are the specialist who knows what you want to your applications.
I jumped to the conclusion that this conversation topic wandered into candidate FPGAs for a BugsBoard transplant. My comments are motivated by the desire to spare adopters time and money, if they wish to perform said transplant (which is not a trivial matter).

On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
> On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
> > On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> > > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > > >
> > > > > > > > e.g. apps/color_toy.py:
> > > > > > > >
> > > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > > >
> > > > > > > > # play with LD0 color
> > > > > > > >
> > > > > > > > ja(fwd('init'))
> > > > > > > >
> > > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > > >
> > > > > > > > # color intensities
> > > > > > > > lbl('red'); data([0])
> > > > > > > > lbl('green'); data([0])
> > > > > > > > lbl('blue'); data([0])
> > > > > > > >
> > > > > > > > # commands
> > > > > > > >
> > > > > > > > lbl('ir') # char -> # increment red
> > > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > > >
> > > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > > >
> > > > > > > > lbl('ig') # char -> # increment green
> > > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > > >
> > > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > > >
> > > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > > >
> > > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > > >
> > > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > > lld(arx_rdy)
> > > > > > > > _if()
> > > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > > drop() # none of the above
> > > > > > > > _then()
> > > > > > > > ret()
> > > > > > > >
> > > > > > > > lbl('init')
> > > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > > _begin()
> > > > > > > > cp(command)
> > > > > > > > lld(red); lst(pwm1)
> > > > > > > > lld(green); lst(pwm2)
> > > > > > > > lld(blue); lst(pwm3)
> > > > > > > > _again()
> > > > > > > >
> > > > > > > > lbl('app_end') # must be on the last line
> > > > > > > >
> > > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > > >
> > > > > > > > Cheers - Myron Plichota
> > > > > > > The number of people who own such a board is probably rather small.
> > > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > > >
> > > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > > This would probably cover as well the related board from Lattice.
> > > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > > >
> > > > > > > Nandland board $65,
> > > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > > FPGA board prices have gone way op over the last few years.
> > > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > > The last time I switched one on, was
> > > > > to verify the CDP1802 that Steve Teal did
> > > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > > All for the fun of it.
> > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > > But:
> > > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > > >
> > > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > > There are so many versions on the website, this one might fit better for you
> > > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> > >
> > > And regarding 0.1" pitch: I have used this solution in the past:
> > > male headers soldered into the board
> > > female header stuck onlo them
> > > short wires soldered to female header
> > > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> > A quick review of the FPGA datasheet shows problems:
> > 1) block RAM lacks separate read and write clocks in single-port mode
> That would be called "semi-dual port" mode.
> > 2) there is a maximum of 26Kx18-bits block RAM available
> Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
> > I do not recommend that board.
> For what?
>
> If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it.. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a serial port.
>
> --
>
> Rick C.
>
> - Get 1,000 miles of free Supercharging
> - Tesla referral code - https://ts.la/richard11209
Popping the stack:
1) Q: do not recommend for what? A: a BugsBoard transplant
2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.

On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
> On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
> > > On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> > > > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > > > >
> > > > > > > > > e.g. apps/color_toy.py:
> > > > > > > > >
> > > > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > > > >
> > > > > > > > > # play with LD0 color
> > > > > > > > >
> > > > > > > > > ja(fwd('init'))
> > > > > > > > >
> > > > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > > > >
> > > > > > > > > # color intensities
> > > > > > > > > lbl('red'); data([0])
> > > > > > > > > lbl('green'); data([0])
> > > > > > > > > lbl('blue'); data([0])
> > > > > > > > >
> > > > > > > > > # commands
> > > > > > > > >
> > > > > > > > > lbl('ir') # char -> # increment red
> > > > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > > > >
> > > > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > > > >
> > > > > > > > > lbl('ig') # char -> # increment green
> > > > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > > > >
> > > > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > > > >
> > > > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > > > >
> > > > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > > > >
> > > > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > > > lld(arx_rdy)
> > > > > > > > > _if()
> > > > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > > > drop() # none of the above
> > > > > > > > > _then()
> > > > > > > > > ret()
> > > > > > > > >
> > > > > > > > > lbl('init')
> > > > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > > > _begin()
> > > > > > > > > cp(command)
> > > > > > > > > lld(red); lst(pwm1)
> > > > > > > > > lld(green); lst(pwm2)
> > > > > > > > > lld(blue); lst(pwm3)
> > > > > > > > > _again()
> > > > > > > > >
> > > > > > > > > lbl('app_end') # must be on the last line
> > > > > > > > >
> > > > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > > > >
> > > > > > > > > Cheers - Myron Plichota
> > > > > > > > The number of people who own such a board is probably rather small.
> > > > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > > > >
> > > > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > > > This would probably cover as well the related board from Lattice.
> > > > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > > > >
> > > > > > > > Nandland board $65,
> > > > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > > > FPGA board prices have gone way op over the last few years.
> > > > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > > > The last time I switched one on, was
> > > > > > to verify the CDP1802 that Steve Teal did
> > > > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > > > All for the fun of it.
> > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > > > But:
> > > > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > > > >
> > > > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > > > There are so many versions on the website, this one might fit better for you
> > > > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> > > >
> > > > And regarding 0.1" pitch: I have used this solution in the past:
> > > > male headers soldered into the board
> > > > female header stuck onlo them
> > > > short wires soldered to female header
> > > > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > > > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> > > A quick review of the FPGA datasheet shows problems:
> > > 1) block RAM lacks separate read and write clocks in single-port mode
> > That would be called "semi-dual port" mode.
> > > 2) there is a maximum of 26Kx18-bits block RAM available
> > Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
> > > I do not recommend that board.
> > For what?
> >
> > If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a serial port.
> >
> > --
> >
> > Rick C.
> >
> > - Get 1,000 miles of free Supercharging
> > - Tesla referral code - https://ts.la/richard11209
> Popping the stack:
> 1) Q: do not recommend for what? A: a BugsBoard transplant
> 2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
> 3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.

On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
> On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
> > On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > > On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
> > > > On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> > > > > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > > > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > > > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > > > > >
> > > > > > > > > > e.g. apps/color_toy.py:
> > > > > > > > > >
> > > > > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > > > > >
> > > > > > > > > > # play with LD0 color
> > > > > > > > > >
> > > > > > > > > > ja(fwd('init'))
> > > > > > > > > >
> > > > > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > > > > >
> > > > > > > > > > # color intensities
> > > > > > > > > > lbl('red'); data([0])
> > > > > > > > > > lbl('green'); data([0])
> > > > > > > > > > lbl('blue'); data([0])
> > > > > > > > > >
> > > > > > > > > > # commands
> > > > > > > > > >
> > > > > > > > > > lbl('ir') # char -> # increment red
> > > > > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > > > > >
> > > > > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > > > > >
> > > > > > > > > > lbl('ig') # char -> # increment green
> > > > > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > > > > >
> > > > > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > > > > >
> > > > > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > > > > >
> > > > > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > > > > >
> > > > > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > > > > lld(arx_rdy)
> > > > > > > > > > _if()
> > > > > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > > > > drop() # none of the above
> > > > > > > > > > _then()
> > > > > > > > > > ret()
> > > > > > > > > >
> > > > > > > > > > lbl('init')
> > > > > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > > > > _begin()
> > > > > > > > > > cp(command)
> > > > > > > > > > lld(red); lst(pwm1)
> > > > > > > > > > lld(green); lst(pwm2)
> > > > > > > > > > lld(blue); lst(pwm3)
> > > > > > > > > > _again()
> > > > > > > > > >
> > > > > > > > > > lbl('app_end') # must be on the last line
> > > > > > > > > >
> > > > > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > > > > >
> > > > > > > > > > Cheers - Myron Plichota
> > > > > > > > > The number of people who own such a board is probably rather small.
> > > > > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > > > > >
> > > > > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > > > > This would probably cover as well the related board from Lattice.
> > > > > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > > > > >
> > > > > > > > > Nandland board $65,
> > > > > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > > > > FPGA board prices have gone way op over the last few years.
> > > > > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > > > > The last time I switched one on, was
> > > > > > > to verify the CDP1802 that Steve Teal did
> > > > > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > > > > All for the fun of it.
> > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > > > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > > > > But:
> > > > > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > > > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > > > > >
> > > > > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > > > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > > > > There are so many versions on the website, this one might fit better for you
> > > > > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> > > > >
> > > > > And regarding 0.1" pitch: I have used this solution in the past:
> > > > > male headers soldered into the board
> > > > > female header stuck onlo them
> > > > > short wires soldered to female header
> > > > > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > > > > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> > > > A quick review of the FPGA datasheet shows problems:
> > > > 1) block RAM lacks separate read and write clocks in single-port mode
> > > That would be called "semi-dual port" mode.
> > > > 2) there is a maximum of 26Kx18-bits block RAM available
> > > Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
> > > > I do not recommend that board.
> > > For what?
> > >
> > > If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a serial port.
> > >
> > > --
> > >
> > > Rick C.
> > >
> > > - Get 1,000 miles of free Supercharging
> > > - Tesla referral code - https://ts.la/richard11209
> > Popping the stack:
> > 1) Q: do not recommend for what? A: a BugsBoard transplant
> > 2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
> > 3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
> Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?
>
> --
>
> Rick C.
>
> +-- Get 1,000 miles of free Supercharging
> +-- Tesla referral code - https://ts.la/richard11209
Please take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.

On Tuesday, December 6, 2022 at 6:47:33 AM UTC-5, Myron Plichota wrote:
> On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
> > On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
> > > On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail..com wrote:
> > > > On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
> > > > > On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> > > > > > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > > > > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > > > > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit....@gmail.com wrote:
> > > > > > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > > > > > >
> > > > > > > > > > > e.g. apps/color_toy.py:
> > > > > > > > > > >
> > > > > > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > > > > > >
> > > > > > > > > > > # play with LD0 color
> > > > > > > > > > >
> > > > > > > > > > > ja(fwd('init'))
> > > > > > > > > > >
> > > > > > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > > > > > >
> > > > > > > > > > > # color intensities
> > > > > > > > > > > lbl('red'); data([0])
> > > > > > > > > > > lbl('green'); data([0])
> > > > > > > > > > > lbl('blue'); data([0])
> > > > > > > > > > >
> > > > > > > > > > > # commands
> > > > > > > > > > >
> > > > > > > > > > > lbl('ir') # char -> # increment red
> > > > > > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('ig') # char -> # increment green
> > > > > > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > > > > > lld(arx_rdy)
> > > > > > > > > > > _if()
> > > > > > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > > > > > drop() # none of the above
> > > > > > > > > > > _then()
> > > > > > > > > > > ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('init')
> > > > > > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > > > > > _begin()
> > > > > > > > > > > cp(command)
> > > > > > > > > > > lld(red); lst(pwm1)
> > > > > > > > > > > lld(green); lst(pwm2)
> > > > > > > > > > > lld(blue); lst(pwm3)
> > > > > > > > > > > _again()
> > > > > > > > > > >
> > > > > > > > > > > lbl('app_end') # must be on the last line
> > > > > > > > > > >
> > > > > > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > > > > > >
> > > > > > > > > > > Cheers - Myron Plichota
> > > > > > > > > > The number of people who own such a board is probably rather small.
> > > > > > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > > > > > >
> > > > > > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > > > > > This would probably cover as well the related board from Lattice.
> > > > > > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > > > > > >
> > > > > > > > > > Nandland board $65,
> > > > > > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > > > > > FPGA board prices have gone way op over the last few years.
> > > > > > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > > > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > > > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > > > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > > > > > The last time I switched one on, was
> > > > > > > > to verify the CDP1802 that Steve Teal did
> > > > > > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > > > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > > > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > > > > > All for the fun of it.
> > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > > > > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > > > > > But:
> > > > > > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > > > > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > > > > > >
> > > > > > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > > > > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > > > > > There are so many versions on the website, this one might fit better for you
> > > > > > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> > > > > >
> > > > > > And regarding 0.1" pitch: I have used this solution in the past:
> > > > > > male headers soldered into the board
> > > > > > female header stuck onlo them
> > > > > > short wires soldered to female header
> > > > > > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > > > > > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> > > > > A quick review of the FPGA datasheet shows problems:
> > > > > 1) block RAM lacks separate read and write clocks in single-port mode
> > > > That would be called "semi-dual port" mode.
> > > > > 2) there is a maximum of 26Kx18-bits block RAM available
> > > > Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
> > > > > I do not recommend that board.
> > > > For what?
> > > >
> > > > If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a serial port.
> > > >
> > > > --
> > > >
> > > > Rick C.
> > > >
> > > > - Get 1,000 miles of free Supercharging
> > > > - Tesla referral code - https://ts.la/richard11209
> > > Popping the stack:
> > > 1) Q: do not recommend for what? A: a BugsBoard transplant
> > > 2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
> > > 3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
> > Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?
> >
> > --
> >
> > Rick C.
> >
> > +-- Get 1,000 miles of free Supercharging
> > +-- Tesla referral code - https://ts.la/richard11209
> Please take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
Meanwhile, hot off the press:
1) lib/sqrt.py:
# integer square root, thanks Wil Baden aka Neil Bawd RIP

On Tuesday, December 6, 2022 at 7:47:33 AM UTC-4, Myron Plichota wrote:
> On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
> > On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
> > > On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail..com wrote:
> > > > On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
> > > > > On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> > > > > > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > > > > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > > > > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit....@gmail.com wrote:
> > > > > > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > > > > > >
> > > > > > > > > > > e.g. apps/color_toy.py:
> > > > > > > > > > >
> > > > > > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > > > > > >
> > > > > > > > > > > # play with LD0 color
> > > > > > > > > > >
> > > > > > > > > > > ja(fwd('init'))
> > > > > > > > > > >
> > > > > > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > > > > > >
> > > > > > > > > > > # color intensities
> > > > > > > > > > > lbl('red'); data([0])
> > > > > > > > > > > lbl('green'); data([0])
> > > > > > > > > > > lbl('blue'); data([0])
> > > > > > > > > > >
> > > > > > > > > > > # commands
> > > > > > > > > > >
> > > > > > > > > > > lbl('ir') # char -> # increment red
> > > > > > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('ig') # char -> # increment green
> > > > > > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > > > > > lld(arx_rdy)
> > > > > > > > > > > _if()
> > > > > > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > > > > > drop() # none of the above
> > > > > > > > > > > _then()
> > > > > > > > > > > ret()
> > > > > > > > > > >
> > > > > > > > > > > lbl('init')
> > > > > > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > > > > > _begin()
> > > > > > > > > > > cp(command)
> > > > > > > > > > > lld(red); lst(pwm1)
> > > > > > > > > > > lld(green); lst(pwm2)
> > > > > > > > > > > lld(blue); lst(pwm3)
> > > > > > > > > > > _again()
> > > > > > > > > > >
> > > > > > > > > > > lbl('app_end') # must be on the last line
> > > > > > > > > > >
> > > > > > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > > > > > >
> > > > > > > > > > > Cheers - Myron Plichota
> > > > > > > > > > The number of people who own such a board is probably rather small.
> > > > > > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > > > > > >
> > > > > > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > > > > > This would probably cover as well the related board from Lattice.
> > > > > > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > > > > > >
> > > > > > > > > > Nandland board $65,
> > > > > > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > > > > > FPGA board prices have gone way op over the last few years.
> > > > > > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > > > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > > > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > > > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > > > > > The last time I switched one on, was
> > > > > > > > to verify the CDP1802 that Steve Teal did
> > > > > > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > > > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > > > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > > > > > All for the fun of it.
> > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > > > > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > > > > > But:
> > > > > > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > > > > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > > > > > >
> > > > > > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > > > > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > > > > > There are so many versions on the website, this one might fit better for you
> > > > > > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> > > > > >
> > > > > > And regarding 0.1" pitch: I have used this solution in the past:
> > > > > > male headers soldered into the board
> > > > > > female header stuck onlo them
> > > > > > short wires soldered to female header
> > > > > > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > > > > > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> > > > > A quick review of the FPGA datasheet shows problems:
> > > > > 1) block RAM lacks separate read and write clocks in single-port mode
> > > > That would be called "semi-dual port" mode.
> > > > > 2) there is a maximum of 26Kx18-bits block RAM available
> > > > Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
> > > > > I do not recommend that board.
> > > > For what?
> > > >
> > > > If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a serial port.
> > > >
> > > > --
> > > >
> > > > Rick C.
> > > >
> > > > - Get 1,000 miles of free Supercharging
> > > > - Tesla referral code - https://ts.la/richard11209
> > > Popping the stack:
> > > 1) Q: do not recommend for what? A: a BugsBoard transplant
> > > 2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
> > > 3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
> > Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?
> >
> > --
> >
> > Rick C.
> >
> > +-- Get 1,000 miles of free Supercharging
> > +-- Tesla referral code - https://ts.la/richard11209
> Please take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.

On Tuesday, December 6, 2022 at 10:51:21 PM UTC-5, gnuarm.del...@gmail.com wrote:
> On Tuesday, December 6, 2022 at 7:47:33 AM UTC-4, Myron Plichota wrote:
> > On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
> > > On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
> > > > On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > > > > On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
> > > > > > On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail..com wrote:
> > > > > > > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > > > > > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > > > > > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > > > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit....@gmail.com wrote:
> > > > > > > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > > > > > > >
> > > > > > > > > > > > e.g. apps/color_toy.py:
> > > > > > > > > > > >
> > > > > > > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > > > > > > >
> > > > > > > > > > > > # play with LD0 color
> > > > > > > > > > > >
> > > > > > > > > > > > ja(fwd('init'))
> > > > > > > > > > > >
> > > > > > > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > > > > > > >
> > > > > > > > > > > > # color intensities
> > > > > > > > > > > > lbl('red'); data([0])
> > > > > > > > > > > > lbl('green'); data([0])
> > > > > > > > > > > > lbl('blue'); data([0])
> > > > > > > > > > > >
> > > > > > > > > > > > # commands
> > > > > > > > > > > >
> > > > > > > > > > > > lbl('ir') # char -> # increment red
> > > > > > > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > > > > > > >
> > > > > > > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > > > > > > >
> > > > > > > > > > > > lbl('ig') # char -> # increment green
> > > > > > > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > > > > > > >
> > > > > > > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > > > > > > >
> > > > > > > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > > > > > > >
> > > > > > > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > > > > > > >
> > > > > > > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > > > > > > lld(arx_rdy)
> > > > > > > > > > > > _if()
> > > > > > > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > > > > > > drop() # none of the above
> > > > > > > > > > > > _then()
> > > > > > > > > > > > ret()
> > > > > > > > > > > >
> > > > > > > > > > > > lbl('init')
> > > > > > > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > > > > > > _begin()
> > > > > > > > > > > > cp(command)
> > > > > > > > > > > > lld(red); lst(pwm1)
> > > > > > > > > > > > lld(green); lst(pwm2)
> > > > > > > > > > > > lld(blue); lst(pwm3)
> > > > > > > > > > > > _again()
> > > > > > > > > > > >
> > > > > > > > > > > > lbl('app_end') # must be on the last line
> > > > > > > > > > > >
> > > > > > > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > > > > > > A link to Bugs18bis.zip is in the downloads section..
> > > > > > > > > > > >
> > > > > > > > > > > > Cheers - Myron Plichota
> > > > > > > > > > > The number of people who own such a board is probably rather small.
> > > > > > > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > > > > > > >
> > > > > > > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > > > > > > This would probably cover as well the related board from Lattice.
> > > > > > > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > > > > > > >
> > > > > > > > > > > Nandland board $65,
> > > > > > > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > > > > > > FPGA board prices have gone way op over the last few years.
> > > > > > > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > > > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > > > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > > > > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > > > > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > > > > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > > > > > > The last time I switched one on, was
> > > > > > > > > to verify the CDP1802 that Steve Teal did
> > > > > > > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > > > > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > > > > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > > > > > > All for the fun of it.
> > > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > > > > > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > > > > > > But:
> > > > > > > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > > > > > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > > > > > > >
> > > > > > > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > > > > > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > > > > > > There are so many versions on the website, this one might fit better for you
> > > > > > > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> > > > > > >
> > > > > > > And regarding 0.1" pitch: I have used this solution in the past:
> > > > > > > male headers soldered into the board
> > > > > > > female header stuck onlo them
> > > > > > > short wires soldered to female header
> > > > > > > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > > > > > > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> > > > > > A quick review of the FPGA datasheet shows problems:
> > > > > > 1) block RAM lacks separate read and write clocks in single-port mode
> > > > > That would be called "semi-dual port" mode.
> > > > > > 2) there is a maximum of 26Kx18-bits block RAM available
> > > > > Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
> > > > > > I do not recommend that board.
> > > > > For what?
> > > > >
> > > > > If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a serial port.
> > > > >
> > > > > --
> > > > >
> > > > > Rick C.
> > > > >
> > > > > - Get 1,000 miles of free Supercharging
> > > > > - Tesla referral code - https://ts.la/richard11209
> > > > Popping the stack:
> > > > 1) Q: do not recommend for what? A: a BugsBoard transplant
> > > > 2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
> > > > 3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
> > > Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?
> > >
> > > --
> > >
> > > Rick C.
> > >
> > > +-- Get 1,000 miles of free Supercharging
> > > +-- Tesla referral code - https://ts.la/richard11209
> > Please take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
> I'm sure there are many things I can spend my time studying. Is there some particular lesson in this file I should be aware of?
>
> --
>
> Rick C.
>
> -- Get 1,000 miles of free Supercharging
> -- Tesla referral code - https://ts.la/richard11209
How 'bout you take a look at it and decide for yourself?

On Thursday, December 8, 2022 at 2:55:02 AM UTC-4, Myron Plichota wrote:
> On Tuesday, December 6, 2022 at 10:51:21 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > On Tuesday, December 6, 2022 at 7:47:33 AM UTC-4, Myron Plichota wrote:
> > > On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail..com wrote:
> > > > On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
> > > > > On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > > > > > On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
> > > > > > > On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> > > > > > > > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > > > > > > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > > > > > > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > > > > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > > > > > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > > > > > > > >
> > > > > > > > > > > > > e.g. apps/color_toy.py:
> > > > > > > > > > > > >
> > > > > > > > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > > > > > > > >
> > > > > > > > > > > > > # play with LD0 color
> > > > > > > > > > > > >
> > > > > > > > > > > > > ja(fwd('init'))
> > > > > > > > > > > > >
> > > > > > > > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > > > > > > > >
> > > > > > > > > > > > > # color intensities
> > > > > > > > > > > > > lbl('red'); data([0])
> > > > > > > > > > > > > lbl('green'); data([0])
> > > > > > > > > > > > > lbl('blue'); data([0])
> > > > > > > > > > > > >
> > > > > > > > > > > > > # commands
> > > > > > > > > > > > >
> > > > > > > > > > > > > lbl('ir') # char -> # increment red
> > > > > > > > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > > > > > > > >
> > > > > > > > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > > > > > > > >
> > > > > > > > > > > > > lbl('ig') # char -> # increment green
> > > > > > > > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > > > > > > > >
> > > > > > > > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > > > > > > > >
> > > > > > > > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > > > > > > > >
> > > > > > > > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > > > > > > > >
> > > > > > > > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > > > > > > > lld(arx_rdy)
> > > > > > > > > > > > > _if()
> > > > > > > > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > > > > > > > drop() # none of the above
> > > > > > > > > > > > > _then()
> > > > > > > > > > > > > ret()
> > > > > > > > > > > > >
> > > > > > > > > > > > > lbl('init')
> > > > > > > > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > > > > > > > _begin()
> > > > > > > > > > > > > cp(command)
> > > > > > > > > > > > > lld(red); lst(pwm1)
> > > > > > > > > > > > > lld(green); lst(pwm2)
> > > > > > > > > > > > > lld(blue); lst(pwm3)
> > > > > > > > > > > > > _again()
> > > > > > > > > > > > >
> > > > > > > > > > > > > lbl('app_end') # must be on the last line
> > > > > > > > > > > > >
> > > > > > > > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > > > > > > > >
> > > > > > > > > > > > > Cheers - Myron Plichota
> > > > > > > > > > > > The number of people who own such a board is probably rather small.
> > > > > > > > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > > > > > > > >
> > > > > > > > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > > > > > > > This would probably cover as well the related board from Lattice.
> > > > > > > > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > > > > > > > >
> > > > > > > > > > > > Nandland board $65,
> > > > > > > > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > > > > > > > FPGA board prices have gone way op over the last few years.
> > > > > > > > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > > > > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > > > > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > > > > > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > > > > > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > > > > > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > > > > > > > The last time I switched one on, was
> > > > > > > > > > to verify the CDP1802 that Steve Teal did
> > > > > > > > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > > > > > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > > > > > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > > > > > > > All for the fun of it.
> > > > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > > > > > > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > > > > > > > But:
> > > > > > > > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > > > > > > > 2) Through-hole pin pitch is not consistently on a 0.1"x0..1" grid, and this is bad for a hobby board.
> > > > > > > > >
> > > > > > > > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > > > > > > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > > > > > > > There are so many versions on the website, this one might fit better for you
> > > > > > > > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> > > > > > > >
> > > > > > > > And regarding 0.1" pitch: I have used this solution in the past:
> > > > > > > > male headers soldered into the board
> > > > > > > > female header stuck onlo them
> > > > > > > > short wires soldered to female header
> > > > > > > > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > > > > > > > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> > > > > > > A quick review of the FPGA datasheet shows problems:
> > > > > > > 1) block RAM lacks separate read and write clocks in single-port mode
> > > > > > That would be called "semi-dual port" mode.
> > > > > > > 2) there is a maximum of 26Kx18-bits block RAM available
> > > > > > Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
> > > > > > > I do not recommend that board.
> > > > > > For what?
> > > > > >
> > > > > > If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a serial port.
> > > > > >
> > > > > > --
> > > > > >
> > > > > > Rick C.
> > > > > >
> > > > > > - Get 1,000 miles of free Supercharging
> > > > > > - Tesla referral code - https://ts.la/richard11209
> > > > > Popping the stack:
> > > > > 1) Q: do not recommend for what? A: a BugsBoard transplant
> > > > > 2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
> > > > > 3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
> > > > Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?
> > > >
> > > > --
> > > >
> > > > Rick C.
> > > >
> > > > +-- Get 1,000 miles of free Supercharging
> > > > +-- Tesla referral code - https://ts.la/richard11209
> > > Please take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
> > I'm sure there are many things I can spend my time studying. Is there some particular lesson in this file I should be aware of?
> >
> > --
> >
> > Rick C.
> >
> > -- Get 1,000 miles of free Supercharging
> > -- Tesla referral code - https://ts.la/richard11209
> How 'bout you take a look at it and decide for yourself?

On Thursday, December 8, 2022 at 3:02:51 AM UTC-5, gnuarm.del...@gmail.com wrote:
> On Thursday, December 8, 2022 at 2:55:02 AM UTC-4, Myron Plichota wrote:
> > On Tuesday, December 6, 2022 at 10:51:21 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > > On Tuesday, December 6, 2022 at 7:47:33 AM UTC-4, Myron Plichota wrote:
> > > > On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
> > > > > On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
> > > > > > On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > > > > > > On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
> > > > > > > > On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> > > > > > > > > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > > > > > > > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit....@gmail.com wrote:
> > > > > > > > > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > > > > > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > > > > > > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > > > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > e.g. apps/color_toy.py:
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > # play with LD0 color
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > ja(fwd('init'))
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > # color intensities
> > > > > > > > > > > > > > lbl('red'); data([0])
> > > > > > > > > > > > > > lbl('green'); data([0])
> > > > > > > > > > > > > > lbl('blue'); data([0])
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > # commands
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > lbl('ir') # char -> # increment red
> > > > > > > > > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > > > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > lbl('ig') # char -> # increment green
> > > > > > > > > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > > > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > > > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > > > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > > > > > > > > lld(arx_rdy)
> > > > > > > > > > > > > > _if()
> > > > > > > > > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > > > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > > > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > > > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > > > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > > > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > > > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > > > > > > > > drop() # none of the above
> > > > > > > > > > > > > > _then()
> > > > > > > > > > > > > > ret()
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > lbl('init')
> > > > > > > > > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > > > > > > > > _begin()
> > > > > > > > > > > > > > cp(command)
> > > > > > > > > > > > > > lld(red); lst(pwm1)
> > > > > > > > > > > > > > lld(green); lst(pwm2)
> > > > > > > > > > > > > > lld(blue); lst(pwm3)
> > > > > > > > > > > > > > _again()
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > lbl('app_end') # must be on the last line
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > BugsBoard_Primer.pdf is at https://drive.google..com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > > > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > Cheers - Myron Plichota
> > > > > > > > > > > > > The number of people who own such a board is probably rather small.
> > > > > > > > > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > > > > > > > > >
> > > > > > > > > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > > > > > > > > This would probably cover as well the related board from Lattice.
> > > > > > > > > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > > > > > > > > >
> > > > > > > > > > > > > Nandland board $65,
> > > > > > > > > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > > > > > > > > FPGA board prices have gone way op over the last few years.
> > > > > > > > > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > > > > > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > > > > > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > > > > > > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > > > > > > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > > > > > > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > > > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > > > > > > > > The last time I switched one on, was
> > > > > > > > > > > to verify the CDP1802 that Steve Teal did
> > > > > > > > > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > > > > > > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > > > > > > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > > > > > > > > All for the fun of it.
> > > > > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > > > > > > > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > > > > > > > > But:
> > > > > > > > > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > > > > > > > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > > > > > > > > >
> > > > > > > > > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > > > > > > > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > > > > > > > > There are so many versions on the website, this one might fit better for you
> > > > > > > > > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> > > > > > > > >
> > > > > > > > > And regarding 0.1" pitch: I have used this solution in the past:
> > > > > > > > > male headers soldered into the board
> > > > > > > > > female header stuck onlo them
> > > > > > > > > short wires soldered to female header
> > > > > > > > > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > > > > > > > > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> > > > > > > > A quick review of the FPGA datasheet shows problems:
> > > > > > > > 1) block RAM lacks separate read and write clocks in single-port mode
> > > > > > > That would be called "semi-dual port" mode.
> > > > > > > > 2) there is a maximum of 26Kx18-bits block RAM available
> > > > > > > Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
> > > > > > > > I do not recommend that board.
> > > > > > > For what?
> > > > > > >
> > > > > > > If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a serial port.
> > > > > > >
> > > > > > > --
> > > > > > >
> > > > > > > Rick C.
> > > > > > >
> > > > > > > - Get 1,000 miles of free Supercharging
> > > > > > > - Tesla referral code - https://ts.la/richard11209
> > > > > > Popping the stack:
> > > > > > 1) Q: do not recommend for what? A: a BugsBoard transplant
> > > > > > 2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
> > > > > > 3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
> > > > > Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?
> > > > >
> > > > > --
> > > > >
> > > > > Rick C.
> > > > >
> > > > > +-- Get 1,000 miles of free Supercharging
> > > > > +-- Tesla referral code - https://ts.la/richard11209
> > > > Please take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
> > > I'm sure there are many things I can spend my time studying. Is there some particular lesson in this file I should be aware of?
> > >
> > > --
> > >
> > > Rick C.
> > >
> > > -- Get 1,000 miles of free Supercharging
> > > -- Tesla referral code - https://ts.la/richard11209
> > How 'bout you take a look at it and decide for yourself?
> Sure, as soon as I find time to look at a random piece of code someone has not said anything about.
>
> Thanks...
>
> --
>
> Rick C.
>
> -+ Get 1,000 miles of free Supercharging
> -+ Tesla referral code - https://ts.la/richard11209
ram1c.v is in the Verilog directory within Bugs18bis.zip. Perhaps you will be the first one to say something about it.

On Thursday, December 8, 2022 at 4:16:38 AM UTC-4, Myron Plichota wrote:
> On Thursday, December 8, 2022 at 3:02:51 AM UTC-5, gnuarm.del...@gmail.com wrote:
> > On Thursday, December 8, 2022 at 2:55:02 AM UTC-4, Myron Plichota wrote:
> > > On Tuesday, December 6, 2022 at 10:51:21 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > > > On Tuesday, December 6, 2022 at 7:47:33 AM UTC-4, Myron Plichota wrote:
> > > > > On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
> > > > > > On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
> > > > > > > On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del....@gmail.com wrote:
> > > > > > > > On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
> > > > > > > > > On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit...@gmail.com wrote:
> > > > > > > > > > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > > > > > > > > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit....@gmail.com wrote:
> > > > > > > > > > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > > > > > > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > > > > > > > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > > > > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > e.g. apps/color_toy.py:
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > # play with LD0 color
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > ja(fwd('init'))
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > # color intensities
> > > > > > > > > > > > > > > lbl('red'); data([0])
> > > > > > > > > > > > > > > lbl('green'); data([0])
> > > > > > > > > > > > > > > lbl('blue'); data([0])
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > # commands
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > lbl('ir') # char -> # increment red
> > > > > > > > > > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > > > > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > lbl('ig') # char -> # increment green
> > > > > > > > > > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > > > > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > > > > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > > > > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > > > > > > > > > lld(arx_rdy)
> > > > > > > > > > > > > > > _if()
> > > > > > > > > > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > > > > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > > > > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > > > > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > > > > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > > > > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > > > > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > > > > > > > > > drop() # none of the above
> > > > > > > > > > > > > > > _then()
> > > > > > > > > > > > > > > ret()
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > lbl('init')
> > > > > > > > > > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > > > > > > > > > _begin()
> > > > > > > > > > > > > > > cp(command)
> > > > > > > > > > > > > > > lld(red); lst(pwm1)
> > > > > > > > > > > > > > > lld(green); lst(pwm2)
> > > > > > > > > > > > > > > lld(blue); lst(pwm3)
> > > > > > > > > > > > > > > _again()
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > lbl('app_end') # must be on the last line
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > > > > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > Cheers - Myron Plichota
> > > > > > > > > > > > > > The number of people who own such a board is probably rather small.
> > > > > > > > > > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > > > > > > > > > This would probably cover as well the related board from Lattice.
> > > > > > > > > > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > > > > > > > > > >
> > > > > > > > > > > > > > Nandland board $65,
> > > > > > > > > > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > > > > > > > > > FPGA board prices have gone way op over the last few years.
> > > > > > > > > > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > > > > > > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > > > > > > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > > > > > > > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > > > > > > > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > > > > > > > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > > > > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > > > > > > > > > The last time I switched one on, was
> > > > > > > > > > > > to verify the CDP1802 that Steve Teal did
> > > > > > > > > > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > > > > > > > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > > > > > > > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > > > > > > > > > All for the fun of it.
> > > > > > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > > > > > > > > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > > > > > > > > > But:
> > > > > > > > > > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > > > > > > > > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > > > > > > > > > >
> > > > > > > > > > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > > > > > > > > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > > > > > > > > > There are so many versions on the website, this one might fit better for you
> > > > > > > > > > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> > > > > > > > > >
> > > > > > > > > > And regarding 0.1" pitch: I have used this solution in the past:
> > > > > > > > > > male headers soldered into the board
> > > > > > > > > > female header stuck onlo them
> > > > > > > > > > short wires soldered to female header
> > > > > > > > > > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > > > > > > > > > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> > > > > > > > > A quick review of the FPGA datasheet shows problems:
> > > > > > > > > 1) block RAM lacks separate read and write clocks in single-port mode
> > > > > > > > That would be called "semi-dual port" mode.
> > > > > > > > > 2) there is a maximum of 26Kx18-bits block RAM available
> > > > > > > > Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
> > > > > > > > > I do not recommend that board.
> > > > > > > > For what?
> > > > > > > >
> > > > > > > > If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a serial port.
> > > > > > > >
> > > > > > > > --
> > > > > > > >
> > > > > > > > Rick C.
> > > > > > > >
> > > > > > > > - Get 1,000 miles of free Supercharging
> > > > > > > > - Tesla referral code - https://ts.la/richard11209
> > > > > > > Popping the stack:
> > > > > > > 1) Q: do not recommend for what? A: a BugsBoard transplant
> > > > > > > 2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
> > > > > > > 3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
> > > > > > Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?
> > > > > >
> > > > > > --
> > > > > >
> > > > > > Rick C.
> > > > > >
> > > > > > +-- Get 1,000 miles of free Supercharging
> > > > > > +-- Tesla referral code - https://ts.la/richard11209
> > > > > Please take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
> > > > I'm sure there are many things I can spend my time studying. Is there some particular lesson in this file I should be aware of?
> > > >
> > > > --
> > > >
> > > > Rick C.
> > > >
> > > > -- Get 1,000 miles of free Supercharging
> > > > -- Tesla referral code - https://ts.la/richard11209
> > > How 'bout you take a look at it and decide for yourself?
> > Sure, as soon as I find time to look at a random piece of code someone has not said anything about.
> >
> > Thanks...
> >
> > --
> >
> > Rick C.
> >
> > -+ Get 1,000 miles of free Supercharging
> > -+ Tesla referral code - https://ts.la/richard11209
> ram1c.v is in the Verilog directory within Bugs18bis.zip. Perhaps you will be the first one to say something about it.

Click here to read the complete article

On Thursday, December 8, 2022 at 3:58:43 AM UTC-5, gnuarm.del...@gmail.com wrote:
> On Thursday, December 8, 2022 at 4:16:38 AM UTC-4, Myron Plichota wrote:
> > On Thursday, December 8, 2022 at 3:02:51 AM UTC-5, gnuarm.del...@gmail.com wrote:
> > > On Thursday, December 8, 2022 at 2:55:02 AM UTC-4, Myron Plichota wrote:
> > > > On Tuesday, December 6, 2022 at 10:51:21 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > > > > On Tuesday, December 6, 2022 at 7:47:33 AM UTC-4, Myron Plichota wrote:
> > > > > > On Tuesday, December 6, 2022 at 2:43:09 AM UTC-5, gnuarm.del...@gmail.com wrote:
> > > > > > > On Monday, December 5, 2022 at 10:04:47 PM UTC-5, Myron Plichota wrote:
> > > > > > > > On Monday, December 5, 2022 at 12:53:15 PM UTC-5, gnuarm.del...@gmail.com wrote:
> > > > > > > > > On Monday, December 5, 2022 at 3:38:14 AM UTC-5, Myron Plichota wrote:
> > > > > > > > > > On Sunday, December 4, 2022 at 10:04:16 AM UTC-5, jpit....@gmail.com wrote:
> > > > > > > > > > > On Sunday, 4 December 2022 at 11:59:54 UTC, Myron Plichota wrote:
> > > > > > > > > > > > On Sunday, December 4, 2022 at 4:26:27 AM UTC-5, jpit...@gmail.com wrote:
> > > > > > > > > > > > > On Saturday, 3 December 2022 at 16:00:41 UTC, James Brakefield wrote:
> > > > > > > > > > > > > > On Saturday, December 3, 2022 at 5:32:00 AM UTC-6, jpit...@gmail.com wrote:
> > > > > > > > > > > > > > > On Wednesday, 30 November 2022 at 12:55:49 UTC, Myron Plichota wrote:
> > > > > > > > > > > > > > > > The hardware is defined in Verilog. The *structured* assembler is written in Python3. Apps source code plays ball with the Python3 foundation.
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > e.g. apps/color_toy.py:
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > include('FPGAburn/appload.py') # must be on the first line
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > # play with LD0 color
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > ja(fwd('init'))
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > lbl('app_msg'); ascii('\r\npress BTN0 to reset')
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > # color intensities
> > > > > > > > > > > > > > > > lbl('red'); data([0])
> > > > > > > > > > > > > > > > lbl('green'); data([0])
> > > > > > > > > > > > > > > > lbl('blue'); data([0])
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > # commands
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > lbl('ir') # char -> # increment red
> > > > > > > > > > > > > > > > drop(); lld(red); inc(); lst(red); ret()
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > lbl('dr') # char -> # decrement red
> > > > > > > > > > > > > > > > drop(); lld(red); dec(); lst(red); ret()
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > lbl('ig') # char -> # increment green
> > > > > > > > > > > > > > > > drop(); lld(green); inc(); lst(green); ret()
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > lbl('dg') # char -> # decrement green
> > > > > > > > > > > > > > > > drop(); lld(green); dec(); lst(green); ret()
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > lbl('ib') # char -> # increment blue
> > > > > > > > > > > > > > > > drop(); lld(blue); inc(); lst(blue); ret()
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > lbl('db') # char -> # decrement blue
> > > > > > > > > > > > > > > > drop(); lld(blue); dec(); lst(blue); ret()
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > lbl('command') # -> # execute a recognized command
> > > > > > > > > > > > > > > > lld(arx_rdy)
> > > > > > > > > > > > > > > > _if()
> > > > > > > > > > > > > > > > lld(uart); dup(); cp(tx) # -> char # echo
> > > > > > > > > > > > > > > > dup(); lbxor(ord('R')); jz(ir)
> > > > > > > > > > > > > > > > dup(); lbxor(ord('r')); jz(dr)
> > > > > > > > > > > > > > > > dup(); lbxor(ord('G')); jz(ig)
> > > > > > > > > > > > > > > > dup(); lbxor(ord('g')); jz(dg)
> > > > > > > > > > > > > > > > dup(); lbxor(ord('B')); jz(ib)
> > > > > > > > > > > > > > > > dup(); lbxor(ord('b')); jz(db)
> > > > > > > > > > > > > > > > drop() # none of the above
> > > > > > > > > > > > > > > > _then()
> > > > > > > > > > > > > > > > ret()
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > lbl('init')
> > > > > > > > > > > > > > > > lit(app_msg); cp(tx_ascii)
> > > > > > > > > > > > > > > > _begin()
> > > > > > > > > > > > > > > > cp(command)
> > > > > > > > > > > > > > > > lld(red); lst(pwm1)
> > > > > > > > > > > > > > > > lld(green); lst(pwm2)
> > > > > > > > > > > > > > > > lld(blue); lst(pwm3)
> > > > > > > > > > > > > > > > _again()
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > lbl('app_end') # must be on the last line
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > BugsBoard_Primer.pdf is at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
> > > > > > > > > > > > > > > > A link to Bugs18bis.zip is in the downloads section.
> > > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > > Cheers - Myron Plichota
> > > > > > > > > > > > > > > The number of people who own such a board is probably rather small.
> > > > > > > > > > > > > > > And cost/availability might be an issue for many who want to give it a go.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > I wonder if the NANDLAND Board / Lattice based could be a target for your software.
> > > > > > > > > > > > > > > This would probably cover as well the related board from Lattice.
> > > > > > > > > > > > > > > https://nandland.com/the-go-board/ has a lot of related documentation to get started.
> > > > > > > > > > > > > > >
> > > > > > > > > > > > > > > Nandland board $65,
> > > > > > > > > > > > > > > https://digilent.com/reference/programmable-logic/cmod-s7/start at $99 and not available at the moment
> > > > > > > > > > > > > > FPGA board prices have gone way op over the last few years.
> > > > > > > > > > > > > > If you are a FPGA beginner and a student and want to avoid using a plug board,
> > > > > > > > > > > > > > the Terasic DE10-Lite and the Realdigital BooleanBoard give you the most for your money.
> > > > > > > > > > > > > > If user IO (buttons, switches and 7-segment display) is not an issue, the Tang Nano 9K deserves a look.
> > > > > > > > > > > > > I had been looking at these low-cost boards at Pimoroni - but out of stock as expected.
> > > > > > > > > > > > > https://shop.pimoroni.com/search?q=fpga%20board
> > > > > > > > > > > > > But I still own many different versions from the past including some of those from Trenz-Electronics that I could use
> > > > > > > > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/ good for breadboards
> > > > > > > > > > > > > The last time I switched one on, was
> > > > > > > > > > > > > to verify the CDP1802 that Steve Teal did
> > > > > > > > > > > > > https://www.amazon.co.uk/FIG-Forth-Manual-Documentation-Test-1802-ebook/dp/B01N42VLJE/ref=sr_1_19?qid=1670145231&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-19
> > > > > > > > > > > > > and this got me to redo the CDP1802 book BMP802 and publish it on amazon as well
> > > > > > > > > > > > > https://www.amazon.co.uk/DESIGN-IDEAS-BOOK-CDP1802-Microprocesor-ebook/dp/B09GWCVHGG/ref=sr_1_10?qid=1670145353&refinements=p_27%3AJuergen+Pintaske&s=books&sr=1-10
> > > > > > > > > > > > > All for the fun of it.
> > > > > > > > > > > > https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE0890-Spartan-7/
> > > > > > > > > > > > This has definite transplant potential. It uses the same XC7S25 FPGA.
> > > > > > > > > > > > But:
> > > > > > > > > > > > 1) I don't see an on-board USB/UART connector. But I see FTDI on the silk screen, which suggests a workaround.
> > > > > > > > > > > > 2) Through-hole pin pitch is not consistently on a 0.1"x0.1" grid, and this is bad for a hobby board.
> > > > > > > > > > > >
> > > > > > > > > > > > The published BugsBoard design is far from holy, e.g. 3 PWM channels are dedicated to drive the on-board RGB LED for fun.
> > > > > > > > > > > > I'd be delighted to hear about succesful mutations on other FPGA-based boards.
> > > > > > > > > > > There are so many versions on the website, this one might fit better for you
> > > > > > > > > > > https://shop.trenz-electronic.de/en/Products/Programmable-Logic/Gowin-LittleBee/
> > > > > > > > > > >
> > > > > > > > > > > And regarding 0.1" pitch: I have used this solution in the past:
> > > > > > > > > > > male headers soldered into the board
> > > > > > > > > > > female header stuck onlo them
> > > > > > > > > > > short wires soldered to female header
> > > > > > > > > > > the other end of the wire soldered onto male header and this stuck into the breadboard.
> > > > > > > > > > > And if this is too wide for a normal breadboard - one breadboard on each side and a lot of space for extensions ...
> > > > > > > > > > A quick review of the FPGA datasheet shows problems:
> > > > > > > > > > 1) block RAM lacks separate read and write clocks in single-port mode
> > > > > > > > > That would be called "semi-dual port" mode.
> > > > > > > > > > 2) there is a maximum of 26Kx18-bits block RAM available
> > > > > > > > > Every part has limitations. Why is 26 blocks of 2k x 18 BRAM a serious limitation? I'm planning to use this part in a design I'm working on.
> > > > > > > > > > I do not recommend that board.
> > > > > > > > > For what?
> > > > > > > > >
> > > > > > > > > If you look at the schematics for this board, it will show the particular FTDI chip used. That will provide a lot of information about how to use it. It has been a couple of years, but I seem to recall that chip can provide both JTAG programming, and a serial port.
> > > > > > > > >
> > > > > > > > > --
> > > > > > > > >
> > > > > > > > > Rick C.
> > > > > > > > >
> > > > > > > > > - Get 1,000 miles of free Supercharging
> > > > > > > > > - Tesla referral code - https://ts.la/richard11209
> > > > > > > > Popping the stack:
> > > > > > > > 1) Q: do not recommend for what? A: a BugsBoard transplant
> > > > > > > > 2) Q: RAM limitation? A: depends on how much (or little) on-chip code and data you have use for
> > > > > > > > 3) semi dual port mode: I noticed that, and the block diagram does not suggest to me that ram1c.v would successfully compile.
> > > > > > > Not sure what you don't like about that file. I don't have time right now to dig into it. Is ram1c.v a file in the project you are talking about, or something from Gowin?
> > > > > > >
> > > > > > > --
> > > > > > >
> > > > > > > Rick C.
> > > > > > >
> > > > > > > +-- Get 1,000 miles of free Supercharging
> > > > > > > +-- Tesla referral code - https://ts.la/richard11209
> > > > > > Please take the time to comprehend ram1c.v in the BugsBoard.zip distro. Perchance it will serve you well. BTW, I never heard about Gowin before this discussion was started.
> > > > > I'm sure there are many things I can spend my time studying. Is there some particular lesson in this file I should be aware of?
> > > > >
> > > > > --
> > > > >
> > > > > Rick C.
> > > > >
> > > > > -- Get 1,000 miles of free Supercharging
> > > > > -- Tesla referral code - https://ts.la/richard11209
> > > > How 'bout you take a look at it and decide for yourself?
> > > Sure, as soon as I find time to look at a random piece of code someone has not said anything about.
> > >
> > > Thanks...
> > >
> > > --
> > >
> > > Rick C.
> > >
> > > -+ Get 1,000 miles of free Supercharging
> > > -+ Tesla referral code - https://ts.la/richard11209
> > ram1c.v is in the Verilog directory within Bugs18bis.zip. Perhaps you will be the first one to say something about it.
> So where do I find this zip file?
>
> --
>
> Rick C.
>
> +- Get 1,000 miles of free Supercharging
> +- Tesla referral code - https://ts.la/richard11209
Bugs18bis.zip is at https://drive.google.com/file/d/1cWZmDik5PlWaEd-srekTiF51chDR8b7_/view?usp=share_link
BTW this link is also in the downloads section of BugsBoard_Primer.pdf at https://drive.google.com/file/d/14iPt_j_lmINSs4cte3_MneA6D4UCBjZi/view?usp=sharing
I tried to convey this info in my kickoff post, but I'm a geek, not a salesman.